Patents by Inventor Ananth Haliyur GOPALAKRISHNA

Ananth Haliyur GOPALAKRISHNA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked common gate finFET devices for area optimization
    Patent number: 9397101
    Abstract: A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: July 19, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: HariKrishna Chintarlapalli Reddy, Jay Madhukar Shah, Ananth Haliyur Gopalakrishna
  • STACKED COMMON GATE FINFET DEVICES FOR AREA OPTIMIZATION
    Publication number: 20150255461
    Abstract: A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.
    Type: Application
    Filed: August 12, 2014
    Publication date: September 10, 2015
    Inventors: HariKrishna CHINTARLAPALLI REDDY, Jay Madhukar SHAH, Ananth Haliyur GOPALAKRISHNA