Patents by Inventor Ananth INDRAKANTI

Ananth INDRAKANTI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263331
    Abstract: A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: February 16, 2016
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Peng Wang, Eric A. Hudson
  • Patent number: 9224618
    Abstract: A method for etching features in an etch layer in a plasma processing chamber is provided. An etch gas is flowed into the plasma processing chamber. A top outer electrode is maintained at a temperature of at least 150° C. during the etching of the features. The etch gas is formed into a plasma, which etches the etch layer.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: December 29, 2015
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ananth Indrakanti, Rajinder Dhindsa
  • Publication number: 20150325479
    Abstract: A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.
    Type: Application
    Filed: July 16, 2015
    Publication date: November 12, 2015
    Inventors: Ananth INDRAKANTI, Peng WANG, Eric A. HUDSON
  • Patent number: 9105700
    Abstract: A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 11, 2015
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Peng Wang, Eric A. Hudson
  • Publication number: 20150170965
    Abstract: A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Applicant: Lam Research Corporation
    Inventors: Ananth INDRAKANTI, Peng WANG, Eric A. HUDSON
  • Patent number: 8906810
    Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
  • Publication number: 20140335697
    Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 13, 2014
    Applicant: Lam Research Corporation
    Inventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
  • Patent number: 8668835
    Abstract: A multi-step etch process wherein elliptical via openings and trench openings are formed in a dielectric layer includes supporting a multi-layer film stack on a temperature controlled electrostatic chuck in a plasma etch reactor. The multi-layer film stack has a dielectric layer and a patterned metal hard mask layer above the dielectric layer. An etchant gas is supplied to the plasma etch reactor. The etchant gas is energized into a plasma state, and via openings in a photo resist are transferred into a planarization layer and then into elliptical portions of the trench openings in a patterned hard mask layer while maintaining the chuck at a temperature of about 30 to 50° C. The elliptical openings are extended into a lower layer of the hard mask and into an underlying dielectric layer while maintaining the chuck at a temperature of 20° C. or below.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: March 11, 2014
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Bhaskar Nagabhirava
  • Publication number: 20130180951
    Abstract: A method for etching features in an etch layer in a plasma processing chamber is provided. An etch gas is flowed into the plasma processing chamber. A top outer electrode is maintained at a temperature of at least 150° C. during the etching of the features. The etch gas is formed into a plasma, which etches the etch layer.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 18, 2013
    Applicant: Lam Research Corporation
    Inventors: Ananth INDRAKANTI, Rajinder DHINDSA