Patents by Inventor Ananth Kamath

Ananth Kamath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Watchdog circuit, circuit, system-on-chip, method of operating a watchdog circuit, method of operating a circuit, and method of operating a system-on-chip
    Patent number: 11544130
    Abstract: A watchdog circuit for monitoring a plurality of virtual machines provided by one core of a plurality of cores. The watchdog circuit may include a first memory portion, a second memory portion, and a control logic configured to count a number of pulses, to, when starting the watchdog circuit, store a global watchdog counter value in the first memory portion, and to store a local counter value for each virtual machine of the one or more virtual machines in the second memory portion, and, after a predefined number of pulses, to modify the global watchdog counter value and the local counter values, and, if the global watchdog counter value fulfills a predefined global watchdog reference criterion or any of the local watchdog counter values fulfills a predefined local watchdog reference criterion, to output an error signal.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: January 3, 2023
    Assignee: Infineon Technologies AG
    Inventors: Sai Kiran Bollu, Ananth Kamath
  • WATCHDOG CIRCUIT, CIRCUIT, SYSTEM-ON-CHIP, METHOD OF OPERATING A WATCHDOG CIRCUIT, METHOD OF OPERATING A CIRCUIT, AND METHOD OF OPERATING A SYSTEM-ON-CHIP
    Publication number: 20210406111
    Abstract: A watchdog circuit for monitoring a plurality of virtual machines provided by one core of a plurality of cores. The watchdog circuit may include a first memory portion, a second memory portion, and a control logic configured to count a number of pulses, to, when starting the watchdog circuit, store a global watchdog counter value in the first memory portion, and to store a local counter value for each virtual machine of the one or more virtual machines in the second memory portion, and, after a predefined number of pulses, to modify the global watchdog counter value and the local counter values, and, if the global watchdog counter value fulfills a predefined global watchdog reference criterion or any of the local watchdog counter values fulfills a predefined local watchdog reference criterion, to output an error signal.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 30, 2021
    Inventors: Sai Kiran Bollu, Ananth Kamath
  • Compensated isolated p-well DENMOS devices
    Patent number: 8604543
    Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath
  • Compensated Isolated P-WELL DENMOS Devices
    Publication number: 20120261766
    Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kamel BENAISSA, Greg C. BALDWIN, Vineet MISHRA, Ananth KAMATH
  • Compensated isolated p-well DENMOS devices
    Patent number: 8232158
    Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: July 31, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath
  • Compensated Isolated P-WELL DENMOS Devices
    Publication number: 20110156144
    Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.
    Type: Application
    Filed: June 28, 2010
    Publication date: June 30, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath