Abstract: A method of designing an integrated circuit (IC) chip is discloses. The method includes designing a higher level comprising a plurality of outputs configured to be connected to inputs in a previously-designed macro level, wherein each input in the macro level includes a configurable filler cell. The method also includes calculating if each input includes an antenna violation based on the higher level and the macro level, and configuring each of the filler cells, wherein each filler cell associated with an antenna violation is configured as an antenna diode.

Abstract: Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.

Abstract: Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.

Abstract: A content addressable memory (CAM) cell system is provided. The CAM cell system includes a first memory cell, a first logic circuitry and a first compare circuitry. The first logic circuit includes a first n-FET, a first p-FET, and a first input terminal. A gate of the first n-FET and a gate of the first p-FET are galvanically coupled to the first input terminal. The first compare circuitry is communicatively coupled to the first memory cell via a first coupling, and to the first input terminal via a second coupling. The first compare circuitry is configured to receive first data stored in the first memory cell via the first coupling, receive first match data, transmit a first binary logical value to the first input terminal via the second coupling in response to the first data not matching the first match data, and transmit a second binary logical value to the first input terminal via the second coupling in response to the first data matching the first match data.

Abstract: A content addressable memory (CAM) cell system is provided. The CAM cell system includes a first memory cell, a first logic circuitry and a first compare circuitry. The first logic circuit includes a first n-FET, a first p-FET, and a first input terminal. A gate of the first n-FET and a gate of the first p-FET are galvanically coupled to the first input terminal. The first compare circuitry is communicatively coupled to the first memory cell via a first coupling, and to the first input terminal via a second coupling. The first compare circuitry is configured to receive first data stored in the first memory cell via the first coupling, receive first match data, transmit a first binary logical value to the first input terminal via the second coupling in response to the first data not matching the first match data, and transmit a second binary logical value to the first input terminal via the second coupling in response to the first data matching the first match data.