Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.

Abstract: A cure catalyst is provided. The cure catalyst may include a Lewis acid and one or both of a nitrogen-containing molecule or a non-tertiary phosphine. The nitrogen-containing molecule may include a mono amine or a heterocyclic aromatic organic compound. A curable composition may include the cure catalyst. An electronic device may include the curable composition. Methods associated with the foregoing are provided also.

Abstract: An underfill composition with enhanced adhesion and improved resistance to cracking comprising an epoxy resin in combination with a difunctional siloxane anhydride epoxy hardener and optional reagents. In some embodiments, the epoxy resin includes a functionalized colloidal silica filler having a particle size ranging from about 1 nm to about 500 nm. The difunctional siloxane anhydride epoxy hardener can optionally be combined with liquid anhydride epoxy hardeners. Cure catalysts, hydroxyl-containing monomers, adhesion promoters, flame retardants and defoaming agents may also be added to the composition. Further embodiments of the present disclosure include packaged solid state devices comprising the underfill compositions.

Abstract: A cure catalyst is provided. The cure catalyst may include a Lewis acid and one or both of a nitrogen-containing molecule or a non-tertiary phosphine. The nitrogen-containing molecule may include a mono amine or a heterocyclic aromatic organic compound. A curable composition may include the cure catalyst. An electronic device may include the curable composition. Methods associated with the foregoing are provided also.

Abstract: A method of forming polymer reinforced solder-bumped containing device or substrate is described. The method comprises the following steps: providing a device or substrate having at least one solder bump formed thereon; coating a predetermined portion of the device or substrate with a curable polymer reinforcement material forming a layer on the device or substrate, partially curing the curable polymer reinforcement material to provide a solder-bumped structure comprising a partially cured polymer reinforcement material, and, making a connection between the solder-bumped structure formed and a printed circuit board or array of attachment pads and fully curing the partially cured polymer reinforcement material to provide a reinforced interconnection. Full curing of the polymer reinforcement material may take place either during the “reflow step” or subsequent to it (post-curing).

Abstract: A curable composition is provided, and a method associated therewith. The curable composition may include a curable resin and a finely divided refractory solid. The solid may have a surface area that is greater than about 5 square meters per gram, and a determined density of active surface termination sites per square nanometer of surface area.

Abstract: A composition for use as underfill material is provided. The underfill material includes a first curable transparent resin composition and a second curable fluxing resin composition. The first curable resin composition includes at least one aromatic epoxy resin in combination with a solvent, a functionalized colloidal silica dispersion, and at least one other component selected from the group consisting of cycloaliphatic epoxy monomers, aliphatic epoxy monomers, hydroxy aromatic compounds and combinations and mixtures thereof, thereby forming a solvent-modified resin. The second curable fluxing composition includes at least one epoxy resin. The combination of the two resin compositions is useful in producing underfill materials and is suitable for use as an encapsulant for electronic chips.

Abstract: An electronic assembly having at least a heat dissipating unit and a heat generating unit is provided. At least one of the heat dissipating unit and the heat generating unit has at least one deliberately modified surface.

Abstract: A finely divided refractory solid and an associated method are provided. The solid may have a surface area that is greater than about 5 square meters per gram. The solid may have a density of active surface termination sites per square nanometer of surface area sufficiently low that a curable composition comprising a curable resin that comprises less than about 99 percent by weight of the solid has a stability ratio of less than about 3 after a period of about two weeks. Also, a curable composition, a cured layer, and an electronic device that includes the cured layer are provided.

Abstract: A curable epoxy formulation comprises an epoxy monomer, an epoxy oligomer, or a combination thereof; an organofunctionalized colloidal silica; a cure catalyst; and optional reagents. Further embodiments of the present invention include a method for making the curable epoxy formulation and a semiconductor package comprising the curable epoxy formulation. Embodiments of cured formulations can have low coefficients of thermal expansion and/or high glass transition temperatures.

Abstract: A composition comprises a first curable resin composition that includes at least one aromatic epoxy resin in combination with a solvent, a functionalized colloidal silica dispersion, and at least one other component selected from the group consisting of cycloaliphatic epoxy monomers, aliphatic epoxy monomers, hydroxy aromatic compounds, combinations thereof, and mixtures thereof. The composition can include a separate second curable fluxing composition that comprises at least one epoxy resin. The first curable resin or the combination of the two resin compositions is useful in producing underfill materials and is suitable for use as an encapsulant for electronic chips.

Abstract: Thermal interface compositions contain filler particles possessing a maximum particle size less than 25 microns in diameter blended with a polymer matrix. Such compositions enable lower attainable bond line thickness, which decreases in-situ thermal resistances that exist between thermal interface materials and the corresponding mating surfaces.

Abstract: A composition for use as underfill material is provided. The underfill material includes a first curable transparent resin composition and a second curable fluxing resin composition. The first curable resin composition includes at least one aromatic epoxy resin in combination with a solvent, a functionalized colloidal silica dispersion, and at least one other component selected from the group consisting of cycloaliphatic epoxy monomers, aliphatic epoxy monomers, hydroxy aromatic compounds and combinations and mixtures thereof, thereby forming a solvent-modified resin. The second curable fluxing composition includes at least one epoxy resin. The combination of the two resin compositions is useful in producing underfill materials and is suitable for use as an encapsulant for electronic chips.

Abstract: An underfill composition with enhanced adhesion and improved resistance to cracking comprising an epoxy resin in combination with a difunctional siloxane anhydride epoxy hardener and optional reagents. In some embodiments, the epoxy resin includes a functionalized colloidal silica filler having a particle size ranging from about 1 nm to about 500 nm. The difunctional siloxane anhydride epoxy hardener can optionally be combined with liquid anhydride epoxy hardeners. Cure catalysts, hydroxyl-containing monomers, adhesion promoters, flame retardants and defoaming agents may also be added to the composition. Further embodiments of the present disclosure include packaged solid state devices comprising the underfill compositions.

Abstract: A solvent-modified resin composition for use as underfill material is provided. The composition having at least one epoxy resin, at least one solvent and a filler of functionalized colloidal silica. The solvent-modified resin composition is useful in making transparent B-stage resin films. Embodiments of the disclosure include use as a wafer level underfill, and an encapsulant for electronic chips.

Abstract: A curable epoxy formulation is provided in the present invention. The formulation comprises an epoxy monomer, an organofunctionalized colloidal silica having a particle size in a range between about 2 nanometers and about 20 nanometers, and optional reagents wherein the organofunctionalized colloidal silica substantially increases the glass transition temperature of the epoxy formulation. Further embodiments of the present invention include a semiconductor package comprising the aforementioned curable epoxy formulation.