Abstract: Embodiments of the disclosure provide a structure including a passive component traversing multiple semiconductor chips, with related systems and methods. A structure of the disclosure includes a plurality of stacked semiconductor chips including a first chip coupled to a second chip through an interface. A passive component traverses the interface between the first chip and the second chip of the plurality of stacked semiconductor chips. The passive component includes a first portion within the first chip and a second portion within the second chip.

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products. During IC design, an electrical netlist with built-in electrical resistance elements (i.e., electrical resistors) is extracted based on an IC design layout. A thermal netlist with built-in thermal resistance elements (i.e., thermal resistors) is automatically extracted based on the electrical netlist. This thermal netlist identifies thermal resistors, external thermal nodes and internal thermal node(s) and does so such that there is one-to-one mapping of the thermal resistors to electrical resistors in the electrical netlist, one-to-one mapping of the external thermal nodes to input, output and power supply nodes in the electrical netlist and one-to-one mapping of the internal thermal node(s) to element(s) (e.g., library and/or customized elements) in the electrical netlist.

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products. During IC design, an electrical netlist with built-in electrical resistance elements (i.e., electrical resistors) is extracted based on an IC design layout. A thermal netlist with built-in thermal resistance elements (i.e., thermal resistors) is automatically extracted based on the electrical netlist. This thermal netlist identifies thermal resistors, external thermal nodes and internal thermal node(s) and does so such that there is one-to-one mapping of the thermal resistors to electrical resistors in the electrical netlist, one-to-one mapping of the external thermal nodes to input, output and power supply nodes in the electrical netlist and one-to-one mapping of the internal thermal node(s) to element(s) (e.g., library and/or customized elements) in the electrical netlist.

Abstract: A variable capacitance semiconductor structure is disclosed. Embodiments include a capacitor having three plates, a top plate, a middle plate, and a bottom plate. The top plate serves as a positive plate. The middle and bottom plates serve as ground plates for the capacitor. A switching circuit selects between the middle plate and the bottom plate for use as the ground plate of the capacitor. The middle plate is slotted, allowing electric fields to penetrate through the middle plate to the bottom plate. The slots prevent the electric fields from terminating at the middle plate. A different capacitance value can be selected, depending on whether the middle plate or bottom plate is selected as the ground plate. Logic circuitry is configured to control the selection of plates to achieve a variety of capacitance values.

Abstract: A variable capacitance semiconductor structure is disclosed. Embodiments include a capacitor having three plates, a top plate, a middle plate, and a bottom plate. The top plate serves as a positive plate. The middle and bottom plates serve as ground plates for the capacitor. A switching circuit selects between the middle plate and the bottom plate for use as the ground plate of the capacitor. The middle plate is slotted, allowing electric fields to penetrate through the middle plate to the bottom plate. The slots prevent the electric fields from terminating at the middle plate. A different capacitance value can be selected, depending on whether the middle plate or bottom plate is selected as the ground plate. Logic circuitry is configured to control the selection of plates to achieve a variety of capacitance values.