Patents by Inventor Anantha Raman Krishnan

Anantha Raman Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9251856
    Abstract: A reader failover system and method are described for a data storage system. At least two reader systems, including a first reader element and a second reader element, situated on the same head, are employed to read a magnetic storage medium. In an aspect, the head is a two-dimensional magnetic recording (TDMR) head. Control circuitry detects when the first reader system provides less than a predetermined performance or fails, and thereafter causes the second reader system, but not the first reader system, to read the magnetic storage medium. In an aspect, a buffer stores a first reader element signal until the control circuitry detects whether or not the first reader element provides less than a predetermined performance or fails. In an aspect, when a reader element fails, data recovery is performed, and all of, or a majority of, the media continues to be readable, improving the data storage system robustness.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: February 2, 2016
    Assignee: Western Digial Technologies, Inc.
    Inventors: David W. Wheelock, Shafa Dahandeh, Anantha Raman Krishnan, Aravind Raghunathan, Kent D. Anderson
  • Patent number: 9214963
    Abstract: A data storage system configured to adaptively code data and related methods are disclosed. In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller includes a channel monitor that determines the quality of read signals from the pages when they are read, and provides adjustment metrics to aid in the selection of a code rate, such as a code rate for a low-density parity-check (LDPC) code. In this way, the code rate used for data encoding can be dynamically adjusted to accommodate degradation of the non-volatile memory array over its useable life.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 15, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shayan S. Garani, Kent D. Anderson, Anantha Raman Krishnan, Guangming Lu, Shafa Dahandeh, Andrew J. Tomlin
  • Patent number: 9059742
    Abstract: In some embodiments of the present invention, a data storage device includes a controller and a memory. The data storage device further includes an LDPC encoder and decoder, with the decoder implementing a dynamic precision-rescaling technique for improving performance. In one embodiment, the technique works by rescaling the binary representations of the input log-likelihood ratios (LLRs) and messages upon activation of decoder-state-based triggers. Various triggering functions are introduced, e.g., checking if the number of output LLRs smaller than a certain limit crosses a threshold, checking if the weight of a syndrome crosses a threshold, etc. This technique offers an improvement in the performance of the decoder.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 16, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kent D. Anderson, Anantha Raman Krishnan
  • Patent number: 9047205
    Abstract: A data storage device is disclosed comprising a non-volatile memory (NVM), wherein data is read from the NVM to generate a two dimension matrix of signal samples, including a first dimension and a second dimension. The matrix of signal samples is first equalized to reduce intersymbol interference (ISI) in the first dimension to generate second dimension signal samples, and second equalized to reduce ISI in the second dimension to generate first dimension signal samples. A first data sequence is detected in response to the first dimension signal samples, and a second data sequence is detected in response to the second dimension signal samples.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 2, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yiming Chen, Anantha Raman Krishnan
  • Patent number: 8990668
    Abstract: Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Anantha Raman Krishnan, Shayan S. Garani, Kent D. Anderson
  • Patent number: 8856615
    Abstract: A data storage device is disclosed comprising a non-volatile memory (NVM). First data is written to a first area of the NVM, and a first estimated data sequence is read from the first area of the NVM. The first estimated data sequence is first decoded, and a log-likelihood ratio (LLR) is first updated based on the first decode. Second data is written to a second area of the NVM, and a second estimated data sequence is read from the second area of the non-volatile memory. The second estimated data sequence is second decoded in response to the first updated LLR, and the LLR is second updated based on the second decode.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: October 7, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Anantha Raman Krishnan, Shayan S. Garani, Kent D. Anderson, Shafa Dahandeh
  • Patent number: 8650451
    Abstract: Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 11, 2014
    Assignee: LSI Corporation
    Inventors: Anantha Raman Krishnan, Nenad Miladinovic, Yang Han, Shaohua Yang
  • Publication number: 20130007551
    Abstract: Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Anantha Raman Krishnan, Nenad Miladinovic, Yang Han, Shaohua Yang
  • Publication number: 20080108893
    Abstract: A method and system for automatically aligning multiple MR volumes in whole-body MR scans is disclosed. The method and system are capable of automatic alignment of leg-volumes in whole-body MR scans that is insensitive to leg movement. In order to align upper and lower MR volumes, an automatic determination may be made that a junction between the upper and lower MR volumes is in a leg region. The lower MR volume is then divided into left and right regions, and each of the left and right regions are independently aligned with the upper MR volume. One of the left and right regions is then adjusted with respect to the other one to compensate for shifting of the legs with respect to each other.
    Type: Application
    Filed: October 29, 2007
    Publication date: May 8, 2008
    Applicant: SIEMENS CORPORATE RESEARCH, INC.
    Inventors: Anantha Raman Krishnan, Li Zhang