Abstract: Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (BAR) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request.

Abstract: Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue in the queue range associated with the queue range ready signal is ready for processing, and a queue process sequencer suitable for determining a queue range ready for processing based on the queue range ready signals, and processing a queue within the queue range determined to be ready for processing.

Abstract: A command is received from a host. It is determined which paths in a plurality of paths are enabled. The type of command and the length associated with the command, if applicable, are determined. A path to use to perform the command is selected from the plurality of paths based at least in part on (1) which paths are determined to be enabled and one or more of the following (2a) the type of the command or (2b) the length associated with the command. The selected path is used to perform the command.

Abstract: A setting associated with a number of command execution units to enable is received at a host controller. The host controller is used to configure a plurality of command execution units so that the number of command execution units specified by the setting are enabled. The enabled command execution units are used to process one or more commands associated with storage.

Abstract: A host access instruction is received from one of a plurality of channels which are served in parallel. The host access instruction includes an address range of one or more addresses and a type of access. The address range and type of access are compared against a table of stored address ranges and stored types of access associated with any pending host access instructions. It is determined whether to execute the host access instruction based at least in part on the comparison. If it is decided to execute the host access instruction, the host access instruction is forwarded for execution and the address range and the type of access from the host access instruction are stored in the table.

Abstract: Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue in the queue range associated with the queue range ready signal is ready for processing, and a queue process sequencer suitable for determining a queue range ready for processing based on the queue range ready signals, and processing a queue within the queue range determined to be ready for processing.

Abstract: Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (BAR) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request.

Abstract: A host access instruction is received from one of a plurality of channels which are served in parallel. The host access instruction includes an address range of one or more addresses and a type of access. The address range and type of access are compared against a table of stored address ranges and stored types of access associated with any pending host access instructions. It is determined whether to execute the host access instruction based at least in part on the comparison. If it is decided to execute the host access instruction, the host access instruction is forwarded for execution and the address range and the type of access from the host access instruction are stored in the table.