Patents by Inventor Anargyros Krikelis
Anargyros Krikelis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11256656Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: GrantFiled: April 27, 2020Date of Patent: February 22, 2022Assignee: Altera CorporationInventors: Michael D. Hutton, Anargyros Krikelis
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Publication number: 20200257651Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Inventors: Michael D. Hutton, Anargyros Krikelis
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Patent number: 10635631Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: GrantFiled: November 9, 2018Date of Patent: April 28, 2020Assignee: Altera CorporationInventors: Michael D. Hutton, Anargyros Krikelis
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Publication number: 20190121783Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: ApplicationFiled: November 9, 2018Publication date: April 25, 2019Inventors: Michael D. Hutton, Anargyros Krikelis
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Patent number: 10127190Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: GrantFiled: November 27, 2017Date of Patent: November 13, 2018Assignee: ALTERA CORPORATIONInventors: Michael D. Hutton, Anargyros Krikelis
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Publication number: 20180089139Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: ApplicationFiled: November 27, 2017Publication date: March 29, 2018Inventors: Michael D. Hutton, Anargyros Krikelis
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Patent number: 9830300Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: GrantFiled: October 7, 2016Date of Patent: November 28, 2017Assignee: ALTERA CORPORATIONInventors: Michael D. Hutton, Anargyros Krikelis
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Publication number: 20170024355Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Inventors: Michael D. Hutton, Anargyros Krikelis
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Publication number: 20160358653Abstract: An integrated circuit die having hardware processing elements with a configurable embedded search engine for a content addressable memory is disclosed. The circuit die includes an area having hardware processor circuits. A search engine is coupled to the circuit die via an interconnection. The search engine receives requests for data content. A content addressable memory is coupled to the search engine. The content addressable memory is searchable by the search engine in response to a search request from the hardware processor circuit for data content.Type: ApplicationFiled: June 8, 2015Publication date: December 8, 2016Inventors: Richard Grenier, Anargyros Krikelis
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Patent number: 9471537Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.Type: GrantFiled: March 14, 2013Date of Patent: October 18, 2016Assignee: Altera CorporationInventors: Michael D. Hutton, Anargyros Krikelis
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Patent number: 9471388Abstract: A hybrid programmable logic is described that performs packet processing functions on received data packets using programmable logic elements, and processors interleaved with the programmable logic elements. The header data may be scheduled for distribution to processing threads associated with the processors by the programmable logic elements. The processors may perform packet processing functions on the header data using both the processing threads and hardware acceleration functions provided by the programmable logic elements.Type: GrantFiled: March 14, 2013Date of Patent: October 18, 2016Assignee: Altera CorporationInventors: Michael D. Hutton, Anargyros Krikelis
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Patent number: 8761188Abstract: In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks. The resulting combination allows for data packets to undergo a processing sequence having the flexibility of software programmability with the high-performance of dedicated hardware. For example, a multi-threaded processor can control the high-level tasks of a processing sequence, while the computationally intensive events (e.g., signal processing filters, matrix operations, etc.) are handled by dedicated hardware blocks.Type: GrantFiled: April 30, 2008Date of Patent: June 24, 2014Assignee: Altera CorporationInventors: Anargyros Krikelis, Martin Roberts
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Patent number: 7096318Abstract: A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel word-organized associative memory having an array of associative memory cells arranged to be capable of bit-parallel search and write operations. A bit-serial associative memory having an array of memory cells arranged to be capable of bit-serial search and write operations, but not word bit-parallel search and write operations, is also included. The bit-serial memory is operatively connected to the bit-parallel memory and arranged to operate as an extension of the same. The method comprises searching the bit-parallel word-organized associative memory and/or the bit-serial associative memory coupled to the bit-parallel memory for data matching search data, and marking the memory cells having stored data matching the search data.Type: GrantFiled: November 21, 2001Date of Patent: August 22, 2006Assignee: Aspex Technology LimitedInventors: Ian Paul Jalowiecki, John Lancaster, Anargyros Krikelis
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Publication number: 20040199724Abstract: A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel word-organized associative memory having an array of associative memory cells arranged to be capable of bit-parallel search and write operations. A bit-serial associative memory having an array of memory cells arranged to be capable of bit-serial search and write operations, but not word bit-parallel search and write operations, is also included. The bit-serial memory is operatively connected to the bit-parallel memory and arranged to operate as an extension of the same. The method comprises searching the bit-parallel word-organized associative memory and/or the bit-serial associative memory coupled to the bit-parallel memory for data matching search data, and marking the memory cells having stored data matching the search data.Type: ApplicationFiled: April 16, 2004Publication date: October 7, 2004Inventors: Ian Paul Jalowiecki, John Lancaster, Anargyros Krikelis