Patents by Inventor Anastasios Katsetos

Anastasios Katsetos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8855401
    Abstract: A method for measuring a dimension of a device includes receiving an image of a portion of the device, receiving a first offset value and a second offset value, processing the image to define a least one graph of a line of pixels, the at least one graph including the brightness level of each pixel in a line of pixels, identifying a location of a first peak and a second peak in the graph, defining a first exclusion area boundary, defining a second exclusion area boundary, setting the brightness level of the pixels between the first exclusion area boundary and the second exclusion area boundary to zero, identifying a first portion of the feature of interest and a second portion of the feature of interest, and measuring a distance between the first portion of the feature of interest and the second portion of the feature of interest.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles N. Archie, Anastasios A. Katsetos, Eric P. Solecky, Georgios A. Vakas
  • Publication number: 20120106824
    Abstract: A method for measuring a dimension of a device includes receiving an image of a portion of the device, receiving a first offset value and a second offset value, processing the image to define a least one graph of a line of pixels, the at least one graph including the brightness level of each pixel in a line of pixels, identifying a location of a first peak and a second peak in the graph, defining a first exclusion area boundary, defining a second exclusion area boundary, setting the brightness level of the pixels between the first exclusion area boundary and the second exclusion area boundary to zero, identifying a first portion of the feature of interest and a second portion of the feature of interest, and measuring a distance between the first portion of the feature of interest and the second portion of the feature of interest.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 3, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles N. Archie, Anastasios A. Katsetos, Eric P. Solecky, Georgios A. Vakas
  • Patent number: 6958621
    Abstract: A recovery circuit and a method for employing the same are provided. The recovery circuit has a current driver and, preferably two pass-gates, a first pass-gate connected in series to the current driver and a second pass-gate connected to a ground. The recovery circuit also has a recovery assembly or element and one or more contacts operatively connecting the recovery circuit to a wearout sensitive circuit or circuit element.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: October 25, 2005
    Assignee: International Business Machines Corporation
    Inventors: Giuseppe La Rosa, Joseph M. Lukaitis, Anastasios A. Katsetos, Stewart E. Rauch, III, Ping-Chuan Wang, Stephen P. Boffoli, Fernando J. Guarin, B. B. (Bob) Lawhorn
  • Publication number: 20050116739
    Abstract: A recovery circuit and a method for employing the same are provided. The recovery circuit has a current driver and, preferably two pass-gates, a first pass-gate connected in series to the current driver and a second pass-gate connected to a ground. The recovery circuit also has a recovery assembly or element and one or more contacts operatively connecting the recovery circuit to a wearout sensitive circuit or circuit element.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 2, 2005
    Inventors: Giuseppe Rosa, Joseph Lukaitis, Anastasios Katsetos, Stewart Rauch, Ping-Chuan Wang, Stephen Boffoli, Fernando Guarin, B. B. Lawhorn
  • Patent number: 6456104
    Abstract: A MOSFET test structure and associated electronics for rapidly heating the MOSFET gate oxide and for applying a stress voltage to the gate. The structure has at least one polysilicon gate with two spaced contacts that permit a heating current to flow through the gate thus rapidly raising the gate temperature to a desired level. External electronics permit applying a measured stress voltage to the gate. The structure is particularly useful in NBTI testing of p-MOSFETs.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Fernando J. Guarin, Anastasios A. Katsetos, Stewart E. Rauch, III