Abstract: Constant pins are determined in a combinational circuit by associating an input of a combinational circuit with a first variable and a second variable, with the second variable being the complement of the first variable. For a first logical cell interconnected to such input, a first mathematical representation and a second mathematical representation are computed. The first mathematical representation is a function of the operation of the first logical cell and a function of the first variable, and the second mathematical representation is a function of the operation of the first logical cell and a function of the second variable. A determination is then made as to whether one of the first and second mathematical representations is equal to a constant.

Abstract: The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the compliment of said first variable, computing for a first logical cell interconnected to said input a first canonical representation, wherein said first canonical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second canonical representation, wherein said second canonical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second canonical representations is equal to zero.

Abstract: The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.

Abstract: The specification discloses a for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.

Abstract: Channels are routed in an integrated circuit layout by reserving grid positions for buffers. Cell pins are identified at different y-coordinates to be connected by the channel. A determination is made as to the necessity of a jog between vertical segments, and if so, a y-coordinate is assigned to each such jog. An x-coordinate is assigned to each channel segment extending across the y-coordinates. Y-coordinates are assigned to buffers to be connected to the channel.

Abstract: A linear assignment problem for an ordered system containing a plurality of boxes each containing an object having an associated penalty function is solved. A hierarchy contains a bottom level containing at least as many generalized boxes as there are boxes in the assignment problem, and top and intermediate levels. The objects of the assignment problem are placed in the generalized box of the top level. A first local task is executed to transition the contents of a generalized box of a higher level to at least two generalized boxes of the next lower level. A second local task is executed on the generalized boxes of the lower level to minimize a global penalty function. The first and second tasks are executed through successive iterations until all of the objects are placed in the generalized boxes in the bottom level in a layout having minimal penalty function.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph.