Abstract: A vector signal generator with direct RF signal synthesis is disclosed. The vector signal generator comprises an RF signal synthesizer, a switch, and a memory. The RF signal synthesizer is configured for converting baseband IQ signals into a modulated digital RF signal. The RF signal synthesizer is connected to an I input, a Q input, a clock input, a control input, and an output, where the clock input is a clock input of the vector signal generator, the control input is a control input of the vector signal generator, and the output is an RF signal output of the vector signal generator. The switch is configured for selecting a source of IQ signals and is connected to an external I input, an external Q input, a stored signal I input, a stored signal Q input, the control input, an I output, and a Q output. The external I input and external Q input are external IQ inputs to the vector signal generator and the I output and the Q output are connected to the I input and the Q input of the RF signal synthesizer.

Abstract: Time variant interleaving equalization of an interleaved analog to digital converter is disclosed. A high-frequency analog input signal is converted into a plurality of individual digital signals using a plurality of interleaved analog-to-digital converters. the plurality of individual digital signals are interleaved into a composite digital signal. The composite digital signal is processed in a time variant interleaving equalizer using a plurality of sets of equalizer coefficients.

Abstract: A periodic signal is sampled. The sampling frequency is less than the Nyquist rate of the periodic signal. A period of the periodic signal is determined. A phase of the periodic signal is tracked to determine a sample's position on the period of the periodic signal. A replica of the periodic signal is reconstructed. A measurement of the periodic signal is determined based on a measurement of the replica of the periodic signal.

Abstract: Time variant interleaving equalization of an interleaved analog to digital converter is disclosed. A high-frequency analog input signal is converted into a plurality of individual digital signals using a plurality of interleaved analog-to-digital converters. the plurality of individual digital signals are interleaved into a composite digital signal. The composite digital signal is processed in a time variant interleaving equalizer using a plurality of sets of equalizer coefficients.

Abstract: Analysis of a read back signal in a magnetic recording device is disclosed. The read back signal is converted to a digital read back signal, and a low frequency component of the digital read back signal is restored. A sample clock is recovered from the restored digital read back signal, and the restored digital read back signal is averaged using the recovered sample clock. A timing error is calculated based at least in part on the averaged restored digital read back signal.

Abstract: Sampling and measuring a periodic signal is disclosed. A periodic signal is sampled. The sampling frequency is less than the Nyquist rate of the periodic signal. A period of the periodic signal is determined. A phase of the periodic signal is tracked to determine a sample's position on the period of the periodic signal. A replica of the periodic signal is reconstructed. A measurement of the periodic signal is determined based on a measurement of the replica of the periodic signal.

Abstract: Analysis of a read back signal in a magnetic recording device is disclosed. The read back signal is converted to a digital read back signal, and a low frequency component of the digital read back signal is restored. A sample clock is recovered from the restored digital read back signal, and the restored digital read back signal is averaged using the recovered sample clock. A timing error is calculated based at least in part on the averaged restored digital read back signal.

Abstract: A method of processing an input broadband signal in RF circuitry includes extracting low-frequency components from the input broadband signal, processing the low-frequency components in low-frequency bypass circuitry, and adding the processed low-frequency components to the output of the RF circuitry to produce a combined output signal. Low-frequency bypass amplifier circuitry for bypassing RF circuitry includes a capacitor having a first terminal for receiving an input signal and a second terminal for connecting to an input of the RF circuitry, and a differential amplifier having two inputs respectively connected to the two terminals of the capacitor, and an output connected to an output of the RF circuitry. High-frequency components of the input signal pass through the capacitor and the RF circuitry, and low-frequency components pass through the differential amplifier and are added to the output of the RF circuitry to produce a combined output signal.

Abstract: A write driver includes two field-effect/bipolar transistors with feedbacks between the drains/collectors and gates/bases, a write/read switch connected between the drains/collectors and a positive power supply, an impedance matching circuit connected to the drains/collectors to match both differential and common mode output impedance of the write driver to an input impedance of a flex circuit, a common mode output voltage control circuit coupled to the transistors, and a differential mode output voltage control circuit coupled to the transistors.

Abstract: A decoder for detecting data within an input signal with attenuated low frequency components that comprises a Viterbi decoder, is disclosed. Viterbi decoder internal data is used along with its output bits to reduce delay between the restored direct current (DC) component and the input signal to zero. As a result, increased accuracy of DC restoration and corresponding bit error rate reduction are achieved.

Abstract: A partial response maximum likelihood (PRML) data detecting in a magnetic recording storage device is carried out with a preliminary measuring of write-read channel responses to all nonzero binary combinations of a given length. Decoding of the user data is performed according to a Viterbi algorithm, where the previously measured responses are used as expected samples for branch metric calculations. The measurement of the write-read channel responses and the decoding of the user data are fulfilled by a self-adjusting PRML receiver that contains a controllable clock recovery, a responses accumulator and an adjustable Viterbi detector. The controllable clock recovery produces a set of read-back signal samples containing exactly one sample per bit with or without phase error correction. The responses accumulator calculates averaged responses of the write-read channel. The adjustable Viterbi detector reconstructs the user data that were written to the disk.

Abstract: A spectrum analyzer with a compensation circuitry for prevention of measurement accuracy deterioration due to local oscillators phase noise.

Abstract: In a signal acquisition system in accordance with the principles of the present invention, a digital signal acquisition system includes a front end, an equalizer and an output system. The front end typically includes an input amplifier and may include one or more preamplifiers, and any one of various input probes. The probes may be directed toward different applications, that is, voltage probes or current probes, for example, and may include preamplifiers that adjust the range of input signals. The output of the probe is typically routed to an input amplifier, which may include various filters and/other signal conditioning circuitry. The system also includes an analog to digital converter that is arranged to receive a conditioned analog input signal from the input amplifier. The analog to digital converter converts the conditioned analog input signal to digitized input signal.

Abstract: A magnetic medium write precompensation circuit produces a precisely controlled delay for magnetic medium write precompensation by digital-to-analog converting a data value, low-pass filtering the digital-to-analog converted signal, and limiting the filtered signal to produce a desired time delay. One or more of the digital-to-analog conversion levels, limiting levels, and filter cutoff levels determines the amount of the delay. Feedback control may be employed to adjust the digital-to-analog conversion level, filtering, and/or the limiting level to thereby adjust the compensation time delay.

Abstract: In a signal acquisition system in accordance with the principles of the present invention, a digital signal acquisition system includes a front end, an equalizer and an output system. The front end typically includes an input amplifier and may include one or more preamplfiers, and any one of various input probes. The probes may be directed toward different applications, that is, voltage probes or current probes, for example, and may include preamplifiers that adjust the range of input signals. The output of the probe is typically routed to an input amplifier, which may include various filters and/other signal conditioning circuitry. The system also includes an analog to digital converter that is arranged to receive a conditioned analog input signal from the input amplifier. The analog to digital converter converts the conditioned analog input signal to digitized input signal.

Abstract: A magnetic medium write precompensation circuit produces a precisely controlled delay for magnetic medium write precompensation by digital-to-analog converting a data value, low-pass filtering the digital-to-analog converted signal, and limiting the filtered signal to produce a desired time delay. One or more of the digital-to-analog conversion levels, limiting levels, and filter cutoff levels determines the amount of the delay. Feedback control may be employed to adjust the digital-to-analog conversion level, filtering, and/or the limiting level to thereby adjust the compensation time delay.

Abstract: A radially distributed transverse filter includes a plurality of delay lines of substantially equal electric length sequentially coupled at a like plurality of nodes. The nodes are distributed equidistant from a common position, for example positioned at vertices of a polygon. A plurality of attenuators are distributed radially about the common position and coupled between the nodes and the common position. An adder is located substantially at the common position for summing the attenuator outputs. In this manner, the respective propagation delays of each tap are substantially similar, and imprecision due to variation in propagation delay is therefore mitigated and/or substantially eliminated. The invention has application to high-frequency digital and analog transverse filters, for example filters for equalizers used in Partial Response Maximum Likelihood (PRML) circuits employed in contemporary magnetic recording systems.

Abstract: The head/disk tester of the invention has a housing 43 that houses spindle 44 that rotatingly supports a magnetic disk 31. The housing supports a moveable carriage 30 that, in turn, supports a magnetic head 32. Positioning means 39 and 41 are used to move the carriage and the magnetic head across the magnetic disk. These positioning means include stepper motors that realize coarse positioning of the magnetic head, and a piezo actuator 37 that is used for fine positioning. Linear encoders 40 and 42 located at both sides of the carriage provide feedback information to a closed-loop positioning system that controls the piezo actuator. A set of special signals ("servo bursts") pre-written at a given track of the magnetic disk is used as an additional source of feedback information for the same closed-loop positioning system. This positioning system includes a servo analyzer 45 that reads and processes servo burst signals from the magnetic disk, and a position controller 49 that controls the piezo actuator.

Abstract: An apparatus for testing magnetic heads and disks comprises a phase locked loop (11) with a phase detector (13) formed by an analog-to-digital converter (40) and a digital-to-analog converter (50). A sine wave signal is supplied to an analog input of an ADC (40) and raw data pulses are supplied to the clock input the of ADC. A phase detector (13) detects deviations in the positions of raw data pulses from the zero crossings of the sine wave signal. A PLL (11) locks in the locations of the zero crossings of the sine wave signal and ADC samples constitute instantaneous values of a bit-shift distribution. These values are processed by a DSP (70). The resulting bit-shift distribution is generated during one disk revolution.