Abstract: A method, apparatus and product for reducing a number of test templates in a test suite. The method comprises determining, for a first test template of the test suite, a first probabilities vector comprising a first plurality of coverage probabilities with respect to a set of coverage events. The method comprises determining, for a second test template of the test suite, a second probabilities vector comprising a second plurality of coverage probabilities with respect to the set of coverage events. The method further comprises determining that the first test template is statistically dominant over the second test template based on the first probabilities vector and based on the second probabilities vector. The method further comprises providing an output based on the determination of the statistically dominant test template.

Abstract: A method, apparatus and product for reducing a number of test templates in a test suite. The method comprises determining, for a first test template of the test suite, a first probabilities vector comprising a first plurality of coverage probabilities with respect to a set of coverage events. The method comprises determining, for a second test template of the test suite, a second probabilities vector comprising a second plurality of coverage probabilities with respect to the set of coverage events. The method further comprises determining that the first test template is statistically dominant over the second test template based on the first probabilities vector and based on the second probabilities vector. The method further comprises providing an output based on the determination of the statistically dominant test template.

Abstract: A method for generating address translation stimuli for post-silicon functional validation is provided. The method includes determining a plurality of memory configurations based on a plurality of translation tables used by a stimuli generator to solve a plurality of test templates, providing a test template from the plurality of test templates, selecting a memory configuration from the plurality of memory configurations based on the test template, a memory variable, and a set of testing parameters, identifying a translation table from the plurality of translation tables based on the test template, allocating a memory space for the translation table, and executing the test template on the stimuli generator based on the translation table, the memory space, and the set of testing parameters.

Abstract: A method for generating address translation stimuli for post-silicon functional validation is provided. The method includes determining a plurality of memory configurations based on a plurality of translation tables used by a stimuli generator to solve a plurality of test templates, providing a test template from the plurality of test templates, selecting a memory configuration from the plurality of memory configurations based on the test template, a memory variable, and a set of testing parameters, identifying a translation table from the plurality of translation tables based on the test template, allocating a memory space for the translation table, and executing the test template on the stimuli generator based on the translation table, the memory space, and the set of testing parameters.

Abstract: Techniques for modifying a circuit are described herein. In some examples, a method includes generating a set of testing data and detecting a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change a physical memory address of the testing data associated with a virtual memory address to a second physical memory address of the testing data. The method can also include generating a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path and transmitting the test template to the circuit for each of a plurality of software instruction threads. Furthermore, the method can include detecting a defect in the execution of the test template by the circuit and modifying the circuit to prevent the defect during execution of the test template.

Abstract: Techniques for modifying a circuit are described herein. In some examples, a method includes generating a set of testing data and detecting a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change a physical memory address of the testing data associated with a virtual memory address to a second physical memory address of the testing data. The method can also include generating a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path and transmitting the test template to the circuit for each of a plurality of software instruction threads. Furthermore, the method can include detecting a defect in the execution of the test template by the circuit and modifying the circuit to prevent the defect during execution of the test template.

Abstract: A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input.

Abstract: An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.

Abstract: A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input.

Abstract: A method, apparatus, and product for partial instruction-by-instruction checking on acceleration platforms. The method comprising: obtaining a trace from an hardware accelerator, wherein the trace is generated by the hardware accelerator during simulation of an execution of a test case on a circuit design; identifying a synchronization point in the trace; simulating execution of the test case by a reference model until reaching the synchronization point; and performing instruction-by-instruction checking in order to identify an error in the circuit design based on the simulated execution by the hardware accelerator, wherein the instruction-by-instruction checking is performed with respect to a portion of the trace that relates to operation after executing the synchronization point, wherein the instruction-by-instruction checking utilizes the reference model to determine an expected outcome of each event recorded in the portion of the trace.

Abstract: Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.

Abstract: Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.

Abstract: An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.

Abstract: Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.

Abstract: A Design-Under-Test (DUT) may be designed to perform speculative execution of a branch path prior to determination whether the branch path is to be performed. Verification of the operation of DUT in respect to the speculative execution is disclosed. A template may be used to generate a plurality of tests. In addition to standard randomness of the tests to various parameters in accordance with the template, the tests may also differ in their respective speculative execution paths. The tests are partitioned by a generator into portions to be placed in speculative paths and portions to be placed in non-speculative paths. The generator may provide for a variance in portions. The generator may provide for nested speculative paths.

Abstract: Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.

Abstract: Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.

Abstract: Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is represented as a directed acyclic graph and then converted into a constraint satisfaction problem. The problem is solved by a CSP engine, and the solution used to generate test cases for execution. Using the model, testing knowledge can be propagated to models applicable to many different designs to produce extensive coverage of address translation mechanisms.

Abstract: A method and system for generating numerical test cases for testing binary floating-point arithmetic units for addition and subtraction operations, in order to verify the proper operation of the units according to a specified standard. The space for eligible test-cases is compatible with masks which stipulate the allowable forms of the operands and the result, including constant as well as variable digits in both the exponent and significand fields. The test-cases, which are generated randomly, cover the entire solution space without excluding any eligible solutions. All standard rounding modes are supported, and if a valid solution does not exist for a given set of masks, this fact is reported. The method is general and can be applied to any standard, such as the IEEE floating-point standard, in any precision.

Abstract: Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is represented as a directed acyclic graph and then converted into a constraint satisfaction problem. The problem is solved by a CSP engine, and the solution used to generate test cases for execution. Using the model, testing knowledge can be propagated to models applicable to many different designs to produce extensive coverage of address translation mechanisms.