Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG.

Abstract: A dynamic power control method and system for resisting multi-user parameter biased aggregation in federated learning are provided; the method includes: (1) establishing a federated learning system model for resisting parameter biased aggregation; (2) constructing a 5 corresponding objective function based on a training purpose of the federated learning system model; (3) introducing, according to the established federated learning system model, a power control factor for resisting user biased gradient aggregation, and determining a corresponding over-the-air computation communication model; (4) processing a signal by a receiver using an incoherent energy detection method without cooperation between the receiver and a transmitter; and (5) determining a federated learning security mechanism method based on resistance against parameter biased aggregation, and completing an updating training process of the federated learning system model.

Abstract: A semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a first electrode and a second electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The third nitride semiconductor layer is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer. The second electrode covers an upper surface of the third nitride semiconductor layer and is in direct contact with the first nitride semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG.

Abstract: An electronic device includes a substrate, a transistor and a doped well. The substrate includes a first region and a second region different from the first region. The transistor is disposed on the first region of the substrate. The transistor includes a first nitride semiconductor layer disposed on the substrate, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer. The second nitride semiconductor layer has a bandgap greater than that of the first nitride semiconductor layer. The doped well is disposed in the second region.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a doped group III-V semiconductor layer and a gate layer. The first nitride semiconductor layer has a first surface. The second nitride semiconductor layer is formed on the first surface of the first nitride semiconductor layer and has a greater bandgap than that of the first nitride semiconductor layer. The doped group III-V semiconductor layer is over the second nitride semiconductor layer. The doped group III-V semiconductor layer includes a first portion and a second portion having different thicknesses. The gate layer is disposed on the first portion and the second portion of the doped group III-V semiconductor layer.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first III-nitride layer, a second III-nitride layer, a first contact layer, a second contact layer, a structure, and a gate layer. The second III-nitride layer is in direct contact with the first III-nitride layer. The first contact layer and the second contact layer are disposed over the second III-nitride layer. The structure is adjacent to an interface of the first III-nitride layer and the second III-nitride layer, and a material of the structure is different from a material of the first III-nitride layer or a material of the second III-nitride layer. The gate layer is disposed between the first contact layer and the second contact layer.

Abstract: The present disclosure discloses a semiconductor component and a method for forming the semiconductor component. The semiconductor component includes a substrate, a III-V layer, a doped III-V layer, a gate contact, a first field plate, and a second field plate. The gate contact has first and second sides away from the doped III-V layer. The first field plate has first and second sides, and the first side is closer to the second side of the gate contact than the second side. The second field plate has first and second sides, and the first side is closer to the second side of the gate contact than the second side. The first field plate is closer to the doped III-V layer than the second field plate and the first side and the second side of the gate contact.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a semiconductor stack and a first ohmic contact. The semiconductor stack is formed on a substrate. The semiconductor stack has a first nitride semiconductor layer and a second nitride semiconductor layer formed on the first nitride semiconductor layer. The second nitride semiconductor layer has a wider bandgap than that of the first nitride semiconductor layer. The first ohmic contact is disposed over the semiconductor stack. The first to ohmic contact has a first opening exposing the first nitride semiconductor layer.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, a first spacer and a second spacer. The second nitride semiconductor layer is formed on the first nitride semiconductor layer and having a greater bandgap than that of the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The first spacer is disposed on the second nitride semiconductor layer. The in second spacer is disposed on the second nitride semiconductor layer and spaced apart from the first spacer by the gate structure. The bottom of the first spacer has a first width, the bottom of the second spacer has a second width, and the first width is different from the second width.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, a first spacer, a second spacer and a drain electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The first spacer is disposed adjacent to a first surface of the gate structure. The second spacer is disposed adjacent to a second surface of the gate structure. The drain electrode is disposed relatively adjacent to the second spacer than the first space. The first spacer has a first length, and the second spacer has a second length greater than the first length along the first direction.

Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer.

Abstract: An electronic device includes a substrate, a transistor and a doped well. The substrate includes a first region and a second region different from the first region. The transistor is disposed on the first region of the substrate. The transistor includes a first nitride semiconductor layer disposed on the substrate, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer. The second nitride semiconductor layer has a bandgap greater than that of the first nitride semiconductor layer. The doped well is disposed in the second region.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a doped group III-V semiconductor layer and a gate layer. The first nitride semiconductor layer has a first surface. The second nitride semiconductor layer is formed on the first surface of the first nitride semiconductor layer and has a greater bandgap than that of the first nitride semiconductor layer. The doped group III-V semiconductor layer is over the second nitride semiconductor layer. The doped group III-V semiconductor layer includes a first portion and a second portion having different thicknesses. The gate layer is disposed on the first portion and the second portion of the doped group III-V semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first III-nitride layer, a second III-nitride layer, a first contact layer, a second contact layer, a structure, and a gate layer. The second III-nitride layer is in direct contact with the first III-nitride layer. The first contact layer and the second contact layer are disposed over the second III-nitride layer. The structure is adjacent to an interface of the first III-nitride layer and the second III-nitride layer, and a material of the structure is different from a material of the first III-nitride layer or a material of the second III-nitride layer. The gate layer is disposed between the first contact layer and the second contact layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG.