Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.

Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.