Patents by Inventor Anda C. Mocuta
Anda C. Mocuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230329612Abstract: Methods, devices, and systems related to determining driver capability are described. In an example, a method can include receiving, at a computing device, data associated with a driver from a sensor, inputting the data into an artificial intelligence (AI) model, performing an AI operation using the AI model, and determining whether the driver is capable of driving a vehicle based on an output of the AI model.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Inventors: Lisa R. Copenspire-Ross, Nkiruka Christian, Trupti D. Gawai, Josephine T. Hamada, Anda C. Mocuta
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Patent number: 9639652Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.Type: GrantFiled: January 6, 2014Date of Patent: May 2, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jae-Eun Park, Kern Rim, Xiaojun Yu
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Patent number: 8997028Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: GrantFiled: April 22, 2013Date of Patent: March 31, 2015Assignee: Mentor Graphics CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Patent number: 8754412Abstract: An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.Type: GrantFiled: January 3, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Xiaojun Yu, Anda C. Mocuta, Toshiaki Kirihata
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Publication number: 20140123097Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jeae-Eun Park, Kern Rim, Xiaojun Yu
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Patent number: 8626480Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.Type: GrantFiled: October 6, 2009Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jae-Eun Park, Kern Rim, Xiaojun Yu
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Publication number: 20130238263Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: ApplicationFiled: April 22, 2013Publication date: September 12, 2013Applicant: Mentor Graphics CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Publication number: 20130168673Abstract: An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.Type: ApplicationFiled: January 3, 2012Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiaojun Yu, Anda C. Mocuta, Toshiaki Kirihata
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Patent number: 8429576Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: GrantFiled: May 15, 2012Date of Patent: April 23, 2013Assignee: Mentor Graphics CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Publication number: 20120227019Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: ApplicationFiled: May 15, 2012Publication date: September 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Patent number: 8239790Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: GrantFiled: August 24, 2011Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Patent number: 8168971Abstract: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.Type: GrantFiled: March 25, 2008Date of Patent: May 1, 2012Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Anda C. Mocuta, Dan M. Mocuta, Carl Radens
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Patent number: 8106462Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.Type: GrantFiled: January 14, 2010Date of Patent: January 31, 2012Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc., Infineon Technologies North America Corp., Chartered Semiconductor Manufacturing Ltd.Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
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Publication number: 20110307846Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: ApplicationFiled: August 24, 2011Publication date: December 15, 2011Applicant: International Business Machines CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Patent number: 8042070Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: GrantFiled: October 23, 2007Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Publication number: 20110169096Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
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Patent number: 7928513Abstract: A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region.Type: GrantFiled: December 22, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Terence B. Hook, Anda C. Mocuta, Jeffrey W. Sleight, Anthony K. Stamper
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Publication number: 20110082680Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.Type: ApplicationFiled: October 6, 2009Publication date: April 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jae-Eun Park, Kern Rim, Xiaojun Yu
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Patent number: 7879650Abstract: In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region.Type: GrantFiled: December 19, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Terence B. Hook, Anda C. Mocuta, Jeffrey W. Sleight, Anthony K. Stamper
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Patent number: 7723750Abstract: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.Type: GrantFiled: July 6, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Effendi Leobandung, Anda C. Mocuta, Dan M. Mocuta