Abstract: A vehicle door assembly comprises an inner door panel, an outer door panel and a mirror assembly. The outer panel is fixed to the inner door panel, the outer door panel having an mounting opening. The mirror assembly is supported to an outer perimeter of the mounting opening of the outer door panel. The mirror assembly has a base bracket and a dampener. The dampener is disposed between the base bracket and at least a portion of the outer perimeter mounting opening of the outer door panel such that the base bracket and the outer door panel are spaced with respect to each other by the dampener.

Abstract: A logistics service system (10) comprising at least one tube (14,16, 43) connecting at least one terminal (11, 12, 70), at least one carrier (17) configured to hold goods (48) to be handled in the logistics service system (10), at least one switching device (51) arranged to connect at least two of said tubes (14, 16, 43), and configured to redirect said carrier (17) from one of said tubes into another of said tubes, at least one means for propulsion (15) of the at least one carrier (17) in said tube (14, 16, 43), at least one control unit (29, 50), and wherein all above being configured to produce logistics services that includes both storing and transport functions.

Abstract: A method of mirroring data to a mirrored to port in a plurality of switches. The method has the steps of determining if data was sent to all of said plurality of switches; determining if said data was sent to a mirrored to port (MTP); and resending said data to all of said plurality of switches if mirroring is enabled and said data was not sent to said MTP.

Abstract: An apparatus and method for enabling functionality of a component, wherein the apparatus includes a random number generating module for generating a random number, and a hash function module in communication with the random number generating module. A host is provided in communication with the random number generating module, and at least one memory in communication with the host is included. An encryption module in communication with the at least one memory is provided, and a comparing device in communication with the encryption module and the hash function module is included. The comparing device of the apparatus compares a first bit string to a second bit string to generate a function enable output for the component.

Abstract: An apparatus and method for enabling functionality of a component, wherein the apparatus includes a random number generating module for generating a random number, and a hash function module in communication with the random number generating module. A host is provided in communication with the random number generating module, and at least one memory in communication with the host is included. An encryption module in communication with the at least one memory is provided, and a comparing device in communication with the encryption module and the hash function module is included. The comparing device of the apparatus compares a first bit string to a second bit string to generate a function enable output for the component.

Abstract: An apparatus and method for enabling functionality of a component, wherein the apparatus includes a random number generating module for generating a random number, and a hash function module in communication with the random number generating module. A host is provided in communication with the random number generating module, and at least one memory in communication with the host is included. An encryption module in communication with the at least one memory is provided, and a comparing device in communication with the encryption module and the hash function module is included. The comparing device of the apparatus compares a first bit string to a second bit string to generate a function enable output for the component.

Abstract: An apparatus and for enabling functionality of a component, wherein the apparatus includes an identification module having an identification number stored therein, and a hash function module in communication with the identification module. A host is provided and is in communication with the identification module, and a guess register in communication with the host is provided. An encryption module is provided and is in communication with the guess register, and a public key module in communication with the encryption module is provided, wherein the public key module has a public key stored therein. A comparator in communication with the encryption module and the hash function module is provided, such that the comparator may compare a first bit string to a second bit string to generate a function enable output for the component.

Abstract: A register file backup system for use with a computer which processes instructions to generate results which thereby change the visual state of the computer. The computer has a register file with a plurality of addressable locations for storing data. The backup system is adapted to return the visual state of the computer to a previous state if an instruction generates an exception. The backup system utilizes less overhead so as to provide easier register file backup than a comparable software or hardware device. The backup system comprises first means for sequentially storing in program order, address information corresponding to destination locations in the register file where instruction results are to be stored.

Abstract: A method of mirroring data to a mirrored to port in a plurality of switches. The method has the steps of determining if data was sent to all of said plurality of switches; determining if said data was sent to a mirrored to port (MTP); and resending said data to all of said plurality of switches if mirroring is enabled and said data was not sent to said MTP.

Abstract: A method of mirroring data to a mirrored to port in a plurality of switches. The method has the steps of determining if data was sent to all of said plurality of switches; determining if said data was sent to a mirrored to port (MTP); and resending said data to all of said plurality of switches if mirroring is enabled and said data was not sent to said MTP.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A method of mirroring data to a mirrored to port in a plurality of switches. The method has the steps of determining if data was sent to all of said plurality of switches; determining if said data was sent to a mirrored to port (MTP); and resending said data to all of said plurality of switches if mirroring is enabled and said data was not sent to said MTP.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

Abstract: A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

Abstract: Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.