Abstract: A digital phase-locked loop (1) has a counter (4) which counts pulses from a voltage controlled oscillator (8). The counter (4) is latched periodically with a period which is determined by an input signal (I) to the counter (4). The latched value is supplied to a compensation unit (5) which deducts a value which approximately corresponds to half the count counted by the counter circuit (4) when the phase lock is locked correctly. The compensated counts are supplied from the output of the compensation unit (5) to an integrator (6) and counter (9) which applies a control signal to the voltage controlled oscillator (8) via a D/A converter.

Abstract: A data transmission system is used for the transmission of a large number of telephone channels between nodes in a transmission network built as a Synchronous Digital Hierarchy (SDH), where a pulse frame (e.g. STM-1) contains a large number of bytes, each of which can be used for the transmission of a telephone channel or of overhead signals for the administration of the system, and where signals from a Plesiochronous Digital Hierarchy (PDH) are introduced into the pulse frame of the Synchronous Digital Hierarchy, so that the signals from the Plesiochronous Digital Hierarchy when introduced do not occupy all the bytes in said pulse frame. At least some of the bytes of the pulse frame which are not occupied by introduction, are used for the transmission of user-specified data signals.

Abstract: A method for desynchronization in a receiver in a digital transmission system, where justification is performed as required by introducing or removing a single bit in the transmitted bit flow on the transmission side when placing telephone calls in the transmission system, and where, on the transmission side, adjustments are moreover made in the transmission system as required by introducing or removing groups of bits in the transmitted bit flow, smooths the effect of the introduced and removed bits in the receiver by the desynchronization. The effect of the introduced and removed bits in the receiver is smoothed in two stages, so that in one stage just the effect originating from said groups of bits is smoothed, and in the other stage just the effect originating from said individual bits is smoothed.