Abstract: A data compression device that serves the purpose of receiving large numbers of bits from inside a microcontroller or device under test which are fed to the data compression device featuring a content addressable memory and associated comparators that will recognize recurring digital data patterns. Each recognized large bit pattern will translate to a small bit numeric value that is output on an encoder output trace port. The trace port refers to the actual physical pins on the outside of the compression device that will be connected to the emulation or tracing instrument recording the sequence of patterns coming out from these very few pins.

Abstract: A system and method for recording a test device's execution flow. The device under test is connected to a programmable hardware recording unit, or disk controller, with a cache memory. Output from the test device, representing the test device's execution flow, is written to a cache memory at the hardware recording unit. Data from the cache memory at the hardware recording unit is drained from the cache memory and written to a large capacity, non-volatile storage device. Execution trace data stored at the storage device may subsequently be reviewed to identify any problems that occurred while the test device was operating.

Abstract: A data compression device that serves the purpose of receiving large numbers of bits from inside a microcontroller or device under test which are fed to the data compression device featuring a content addressable memory and associated comparators that will recognize recurring digital data patterns. Each recognized large bit pattern will translate to a small bit numeric value that is output on an encoder output trace port. The trace port refers to the actual physical pins on the outside of the compression device that will be connected to the emulation or tracing instrument recording the sequence of patterns coming out from these very few pins.