Abstract: A phase interpolator to receive a first and a second input clock with a first and a second input clock edge comprises an interpolating circuit unit comprising: resistors in parallel; for each resistor, a connecting switch to connect and disconnect, as operated in accordance with one of the first and the second input clocks, the resistor to and from a first supply line; and a capacitor in series with the resistors. The phase interpolator allow controlling a partial group of the connecting switches to be operated in accordance with the first input clock, and controlling the rest of the connecting switches to be operated in accordance with the second input clock; and determine the output clock of the phase interpolator on the basis of an output signal of the interpolating circuit unit, defined by the voltage over the capacitor after the second input clock edge.

Abstract: A phase interpolator to receive a first and a second input clock with a first and a second input clock edge comprises an interpolating circuit unit comprising: resistors in parallel; for each resistor, a connecting switch to connect and disconnect, as operated in accordance with one of the first and the second input clocks, the resistor to and from a first supply line; and a capacitor in series with the resistors. The phase interpolator allow controlling a partial group of the connecting switches to be operated in accordance with the first input clock, and controlling the rest of the connecting switches to be operated in accordance with the second input clock; and determine the output clock of the phase interpolator on the basis of an output signal of the interpolating circuit unit, defined by the voltage over the capacitor after the second input clock edge.

Abstract: A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY1 at a first point t1 in time and a second delay signal SDLY2 at a second point in time t2. The sampler module is configured to provide a first sample S1 of the oscillator output signal SOUT at the first point in time t1 and a second sample S2 of the oscillator output signal SOUT at the second point in time t2. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S1 and the second sample S2. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.

Abstract: A phase interpolator to receive a first and a second input clock with a first and a second input clock edge comprises an interpolating circuit unit comprising: resistors in parallel; for each resistor, a connecting switch to connect and disconnect, as operated in accordance with one of the first and the second input clocks, the resistor to and from a first supply line; and a capacitor in series with the resistors. The phase interpolator allow controlling a partial group of the connecting switches to be operated in accordance with the first input clock, and controlling the rest of the connecting switches to be operated in accordance with the second input clock; and determine the output clock of the phase interpolator on the basis of an output signal of the interpolating circuit unit, defined by the voltage over the capacitor after the second input clock edge.

Abstract: A phase interpolator to receive a first and a second input clock with a first and a second input clock edge comprises an interpolating circuit unit comprising: resistors in parallel; for each resistor, a connecting switch to connect and disconnect, as operated in accordance with one of the first and the second input clocks, the resistor to and from a first supply line; and a capacitor in series with the resistors. The phase interpolator allow controlling a partial group of the connecting switches to be operated in accordance with the first input clock, and controlling the rest of the connecting switches to be operated in accordance with the second input clock; and determine the output clock of the phase interpolator on the basis of an output signal of the interpolating circuit unit, defined by the voltage over the capacitor after the second input clock edge.

Abstract: A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY1 at a first point t1 in time and a second delay signal SDLY2 at a second point in time t2. The sampler module is configured to provide a first sample S1 of the oscillator output signal SOUT at the first point in time t1 and a second sample S2 of the oscillator output signal SOUT at the second point in time t2. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S1 and the second sample S2. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.

Abstract: A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal (SDLY1) at a first point (t1) in time and a second delay signal (SDLY2) at a second point in time (t2). The sampler module is configured to provide a first sample (S1) of the oscillator output signal (SOUT) at the first point in time (t1) and a second sample (S2) of the oscillator output signal (SOUT) at the second point in time (t2). The interpolator is configured to provide a sampler signal (SSAMPL) by interpolating the first sample (S1) and the second sample (S2). The voltage controlled oscillator is configured to control the oscillator output signal (SOUT) based on the sampler signal (SSAMPL).

Abstract: A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal (SDLY1) at a first point (t1) in time and a second delay signal (SDLY2) at a second point in time (t2). The sampler module is configured to provide a first sample (S1) of the oscillator output signal (SOUT) at the first point in time (t1) and a second sample (S2) of the oscillator output signal (SOUT) at the second point in time (t2). The interpolator is configured to provide a sampler signal (SSAMPL) by interpolating the first sample (S1) and the second sample (S2). The voltage controlled oscillator is configured to control the oscillator output signal (SOUT) based on the sampler signal (SSAMPL).

Abstract: A handheld, small but accurate and reliable device for diagnostic NO measurements using a NO sensor, where the parameters governing the taking of the sample are different from the parameters optimal for the accuracy of said NO sensor. By temporarily storing a portion of the exhaled air, and feeding this to the sensor at a flow rate adapted to the NO sensor, the accuracy and sensitivity of a system/method involving NO sensors, in particular electrochemical NO sensors, can be increased. The method for diagnostic NO measurements comprises steps for controlling the inhalation of NO free air, as well as the exhalation, both by built-in means and by audible and/or visual feedback to the patient.

Abstract: A handheld, small but accurate and reliable device for diagnostic NO measurements using a NO sensor, where the parameters governing the taking of the sample are different from the parameters optimal for the accuracy of said NO sensor. By temporarily storing a portion of the exhaled air, and feeding this to the sensor at a flow rate adapted to the NO sensor, the accuracy and sensitivity of a system/method involving NO sensors, in particular electrochemical NO sensors, can be increased. The method for diagnostic NO measurements comprises steps for controlling the inhalation of NO free air, as well as the exhalation, both by built-in means and by audible and/or visual feedback to the patient.

Abstract: An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digital circuits. Each clock dithering circuit is configured to dither flanks of a respective first and second clock input signal, and generate a dithered clock output signal, one for each of the sigma-delta modulator and digital circuits. A frequency of each dithered clock output signal follows a frequency of the respective first and second clock input signals, and a phase between each dithered clock output signal and the respective first and second clock input signal is shifted and constantly changing.

Abstract: An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digital circuits. Each clock dithering circuit is configured to dither flanks of a respective first and second clock input signal, and generate a dithered clock output signal, one for each of the sigma-delta modulator and digital circuits. A frequency of each dithered clock output signal follows a frequency of the respective first and second clock input signals, and a phase between each dithered clock output signal and the respective first and second clock input signal is shifted and constantly changing.

Abstract: A handheld, small but accurate and reliable device for diagnostic NO measurements using a NO sensor, where the parameters governing the taking of the sample are different from the parameters optimal for the accuracy of said NO sensor. By temporarily storing a portion of the exhaled air, and feeding this to the sensor at a flow rate adapted to the NO sensor, the accuracy and sensitivity of a system/method involving NO sensors, in particular electrochemical NO sensors, can be increased. The method for diagnostic NO measurements comprises steps for controlling the inhalation of NO free air, as well as the exhalation, both by built-in means and by audible and/or visual feedback to the patient.

Abstract: A handheld, small but accurate and reliable device for diagnostic NO measurements using a NO sensor, where the parameters governing the taking of the sample are different from the parameters optimal for the accuracy of said NO sensor I described. By temporarily storing a portion of the exhaled air, and feeding this to the sensor at a flow rate adapted to the NO sensor, the accuracy and sensitivity of a system/method involving NO sensors, in particular electrochemical NO sensors, can be increased. The method for diagnostic NO measurements comprises steps for controlling the inhalation of NO free air, as well as the exhalation, both by built-in means and by audible and/or visual feedback to the patient.

Abstract: A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.

Abstract: A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.

Abstract: Arrangement in a blower including at least an engine and a fan, the fan includes a fan housing enclosing a fan wheel and a fan inlet. The engine and fan are surrounded by a casing provided with an air inlet to let air in to the fan inlet placed inside the casing. The air stream from the air inlet in the housing to the fan inlet cools the engine and components inside the casing before it enters the fan inlet and leaves the blower via a blower tube. The fan housing is provided with an opening (31) placed in the fan housing so that air is allowed to leave the fan in case of blocked air stream in the fan outlet or blower tube.

Abstract: A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) (52) comprising a voltage controlled oscillator (VCO) (53) controlled by means of a tuning voltage (Vtune) is disclosed.

Abstract: There is provided a method for monitoring a building control device, the method comprising associating the building control device with an event; storing the event and at least one parameter of the building control device in a database, wherein the database is operatively connected to a plurality of operator devices, and wherein the at least one parameter at least pertains to defining the event to be one from the group of unassigned, pending, or assigned by the plurality of operator devices; traversing, by at least a first of the plurality of operator devices, the database subject to the at least one parameter.

Abstract: A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.