Abstract: The disclosure relates to a method and apparatus for noise suppression in an LVDS receiver by providing improved common mode noise immunity through a bypass circuit. In one embodiment, the disclosure relates to an apparatus for providing Low Voltage Differential signaling (LVDS). The apparatus includes a preamplifier circuit for receiving a DC component of a first signal and providing a first processed DC signal; a first bypass circuit for receiving an AC component of the first signal, the first bypass circuit providing a first AC output signal; a first node for combining the processed DC signal with the first AC output signal to form a first combined output signal; and an amplifier circuit for amplifying the first combined output signal and a second signal to provide a first amplified signal and a second amplified signal, wherein the first bypass circuit is in parallel with the preamplifier circuit.

Abstract: Disclosed is a transimpedance amplifier comprising a multistage amplifier and a feedback circuit coupled between a single ended input terminal and one of a plurality of differential output terminals of the multistage amplifier. The feedback circuit may control an input voltage at the single input terminal to substantially maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

Abstract: Disclosed is a transimpedance amplifier comprising a multistage amplifier and a feedback circuit coupled between a single ended input terminal and one of a plurality of differential output terminals of the multistage amplifier. The feedback circuit may control an input voltage a the single input terminal to substantially maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

Abstract: Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data.