Abstract: To minimize power dissipation in a line driver (3) in a central office (CO) for driving a DSL connection to a network terminal (NT) with a predetermined maximum constellation size, the central office (CO) supplies the line driver (3) with a predetermined supply voltage during a training sequence, and transfers data with a predetermined power spectral density in all available channels. The network terminal (NT) measures the signal-to-noise ratio of each channel, and transfers information to the central office (CO) about channels having signal-to-noise ratios that enable transfer of data.

Abstract: The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.

Abstract: An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and the highly doped layer is doped with the same type of dopant as the buried collector, but to a lower concentration. The sub-layer causes a more even distribution of the potential lines in the substrate and in a sub-collector layer, thereby eliminating areas of dense potential lines and increasing the breakdown voltage of the component, (i.e., because the breakdown voltage is lower in areas with dense potential lines).

Abstract: A high-voltage MOS transistor is produced in a low-voltage CMOS process without adding extra process steps for producing the high-voltage MOS For. The high-voltage MOS transistor is to be used as an analog line driver and is produced on tho same silicon area as low voltage AD/DA-converters. Hereby, the low-voltage and the high-voltage design block are directly compatible with each other, e.g. have the same threshold voltages, which simplifies the design of the total solution.

Abstract: A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schotty barriers or pn-hereto-barriers and distributing X particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputted layer.

Abstract: A high-voltage MOS transistor is produced in a low-voltage CMOS process without adding extra process steps for producing the high-voltage MOS transistor. The high-voltage MOS transistor is to be used as an analog line driver and is produced on the same silicon area as low voltage AD/DA- converters. Hereby, the low-voltage and the high-voltage design block are directly compatible with each other, e.g. have the same threshold voltages, which simplifies the design of the total solution.

Abstract: The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.

Abstract: A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall. The dopants will diffuse through the layer and form a low resistance connection to the buried layer. The layer may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer is not in itself conducting, the size of the component may be significantly reduced.

Abstract: To minimize power dissipation in a line driver (3) in a central office (CO) for driving a DSL connection to a network terminal (NT) with a predetermined maximum constellation size, the central office (CO) supplies the line driver (3) with a predetermined supply voltage during a training sequence, and transfers data with a predetermined power spectral density in all available channels. The network terminal (NT) measures the signal-to-noise ratio of each channel, and transfers information to the central office (CO) about channels having signal-to-noise ratios that enable transfer of data.

Abstract: A conductor 1 crossing a trench around an electrical component 1 is electrically connected to an isolated intermediate conducting region in order to move the field strength concentrations out of the electrical component and into the intermediate conducting region. This prevents avalanche breakdown occurring in the electrical component.

Abstract: A high-voltage MOS transistor is produced in a low-voltage CMOS process without adding extra process steps for producing the high-voltage MOS transistor. The high-voltage MOS transistor is to be used as an analog line driver and is produced on the same silicon area as low voltage AD/DA- converters. Hereby, the low-voltage and the high-voltage design block are directly compatible with each other, e.g. have the same threshold voltages, which simplifies the design of the total solution.

Abstract: A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schottky barriers or pn-hetero-barriers and distributing the particles so that the depletion regions then produced around neighboring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputtered layer.

Abstract: A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schottky barriers or pn-hetero-barriers and distributing the particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputtered layer.

Abstract: A manufacturing method for semiconductor components is disclosed which will allow better precision in the definition of the doped areas of the components and the separation of differently doped areas. A selectively shaped area of, for example, polysilicon, defining the area or areas to be doped, is deposited on the component before the masks are applied. This makes the fitting of the masks less critical, as they only have to be fitted within the area of the polysilicon layer. In this way an accuracy of 0.1 .mu.m or better can be achieved.

Abstract: A manufacturing method for semiconductor components is disclosed which will allow better precision in the definition of the doped areas of the components and the separation of differently doped areas. A selectively shaped area of, for example, polysilicon, defining the area or areas to be doped, is deposited on the component before masks are applied. This makes the positioning of masks less critical because they only have to be positioned within the area of the polysilicon layer. In this way, an accuracy of 0.1 .mu.m or better can be achieved.

Abstract: A conductor crossing a trench around an electrical component is electrically connected to an isolated intermediate conducting region in order to move the field strength concentrations out of the electrical component and into the intermediate conducting region. This prevents avalanche breakdown from occurring in the electrical component.

Abstract: Method for improving the topography over trench structures in which the provision of extra poly-semiconductor material e.g. polysilicon or nitrate or oxide in the regions of the trench edges and, if necessary, the subsequent oxidation of the extra material prevents the occurrence of regions of high mechanical stress.

Abstract: The invention relates to a semiconductor device and a method in this device, wherein the semiconductor device operates completely or partly in lateral extension. The semiconductor device comprises at least two high-voltage lateral bipolar transistors with at least two mutually opposite emitter/base regions, which are placed at the surface of the epi-taxial layer at a mutual distance such that an intermediate common collector region is formed. The common collector region can be completely depleted when the device has a voltage applied and by using a lateral depletion of said collector region, the voltage durability of the semiconductor device can be determined lithographically by the distance between the doped regions comprised in the device. Furthermore, undesired parasitic components, which are dependent on the quality of the active layer of the device, resistivity and substrate potential, can be eliminated or suppressed.

Abstract: In order to avoid thermal runaway bipolar transistors, emitters are provided with ballast resistors. Elongate ballast resistors may be used, part of the lengths being connected for obtaining suitable resistance and design variability. The emitters are split up into a plurality of emitter portions, each with a separate emitter ballast resistor. The collector and base are correspondingly split up. The transistor is split up into unit cells, each comprising an emitter, a ballast resistor, a base, and a collector, which are respectively connected via respective common leads. This structure may advantageously be realized in a SOI technique, the galvanic isolation enabling unproblematic mixing of digital and analog and power devices in the same chip.

Abstract: An island of material has an insulating trench structure. The trench structure includes a first insulating trench surrounded by a second insulating trench. The trenches are joined together by at least two transverse linking trenches.