Abstract: Aggressive pipelining allows Field Programmable Gate Arrays (FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. A reformulation of saturated addition as an associative operation permits a parallel-prefix calculation to be used to perform saturated accumulation at any data rate supported by the device. The method may be extended to other operations containing loops with one or more loop-carried dependencies.

Abstract: An apparatus and methods for interconnecting a plurality of nanoscale programmable logic array (PLA) clusters are disclosed. The appartus allows PLA clusters to be built at nanoscale dimensions, signal restoration to occur at the nanoscale, and interconnection between PLA clusters to be performed with nanoscale wiring. The nanoscale PLA, restoration, and interconnect arrangements can be constructed without using lithographic patterning to produce the nanoscale feature sizes and wire pitches. The nanoscale interconnection of the plurality of nanoscale PLA clusters can implement any logic function or any finite state machine. The nanoscale interconnect allows Manhattan (X,Y grid) routing between arbitrary nanoscale PLA clusters. The methods teach how to interconnect nanoscale PLAs with nanoscale interconnect and how to build arbitrary logic with nanoscale feature sizes without using lithography to pattern the nanoscale features.

Abstract: An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscale wires.

Abstract: An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscale wires.

Abstract: A memory array comprising nanoscale wires is disclosed. The nanoscale wires are addressed by means of controllable regions axially and/or radially distributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires and microscale wires. In a two-dimensional embodiment, memory locations are defined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires located in different vertical layers.

Abstract: A method for controlling electric conduction on nanoscale wires is disclosed. The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows or prevents electric conduction on the controlled nanoscale wires. The controllable regions are of two different types. For example, a first type of controllable region can exhibit a different doping from a second type of controllable region. The method allows one or more of a set of nanoscale wires, packed at sublithographic pitch, to be independently selected.

Abstract: A network for interconnecting processing element nodes which supports rich interconnection while having a number of switching elements which is linear in the number of processing elements interconnected. Processing elements connect to the lowest level of the tree and the higher levels of the tree make connections between the processing elements. The processing elements may be laid out in a two dimensional grid and one or more horizontal and vertical trees may be used to connect between the processing elements with corner switches used to connect between the horizontal and vertical trees. The levels of the tree can be accommodated in multiple layers of metalization such that the entire layout requires a two-dimensional area which is linear in the number of processing elements supported.

Abstract: An apparatus and methods for a sublithographic programmable logic array (PLA) are disclosed. The apparatus allows combination of non-restoring, programmable junctions and fixed (non-programmable) restoration logic to implement any logic function or any finite-state machine. The methods disclosed teach how to integrate fixed, restoration logic at sublithographic scales along with programmable junctions. The methods further teach how to integrate addressing from the microscale so that the nanoscale crosspoint junctions can be programmed after fabrication.

Abstract: A method and a device for performing placement of a plurality of elements for circuit design. A potential location is assigned to each element and a placement engine is assigned to each potential location. Pairing operations are performed, in parallel, between placement engines to determine whether to perform exchange of the elements associated with the engines. Exchange determination is based both on a cost function and on randomness considerations. Also self-placement is allowed, where the placement engines are implemented on the same hardware system on which the elements are to be placed.

Abstract: A method for controlling electric conduction on nanoscale wires is disclosed. The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows or prevents electric conduction on the controlled nanoscale wires. The controllable regions are of two different types. For example, a first type of controllable region can exhibit a different doping from a second type of controllable region. The method allows one or more of a set of nanoscale wires, packed at sublithographic pitch, to be independently selected.

Abstract: A memory array comprising nanoscale wires is disclosed. The nanoscale wires are addressed by means of controllable regions axially and/or radially distributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires and microscale wires. In a two-dimensional embodiment, memory locations are defined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires located in different vertical layers.

Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Abstract: An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscale wires.

Abstract: A fast router and a fast hardware-assisted routing method are disclosed in a network having endpoints, switches and interconnect links. The switches are programmable to allow endpoints to be connected through a particular configuration of switches. The switches also comprise: propagation circuitry which allows a search signal to be propagated through the network; allocation circuitry to set the configuration of switches once a path has been found; and deallocation circuitry to clear a configuration of switches once no path has been found.

Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Abstract: A single chip microprocessor or memory device has reprogrammable characteristics according to the invention. In the case of the microprocessor, a fixed processing cell is provided as is common to perform logic calculations. A portion of the chip silicon real-estate, however, is dedicated a programmable gate array. This feature enables application-specific configurations to allow adaptation to the particular time-changing demands of the microprocessor and provide the functionality required to best serve those demands. This yields application acceleration and in system-specific functions. In other cases the configurable logic acts as network interface, which allows the same basic processor design to function in any environment to which the interface can adapt.The invention also concerns a memory device having a plurality of memory banks and configurable logic units associated with the memory banks. An interconnect is provided to enable communication between the configurable logic units.

Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Abstract: An integrated dynamically programmable gate array comprises a two dimensional array of programmable gates. These gates can be implemented as look up tables but hardwired gates with programmable interconnections are also possible. Each one of the gates receives plural input logic signals from plural other gates. Consequently, a broad range of logic combinations are possible. The gates further include locally stored multiple contexts dictating different combinatorial logic operations performed by the gates. The contexts increase the logic operations performable by the gate and the fact that the contexts are locally stored enables better integration and speed. Only a context instruction needs to be distributed among programmable gates. A context signal generator is included that generates a context signal indicating a change in an active one of the contexts. This active context dictates the logic operations of the gates that commonly receive by the signal.