Abstract: The invention relates to a system for testing the failure or satisfactory operation of a logic component circuit.The system comprises a generator, whose outputs are respectively connected to the simulation inputs of the components, in order to apply thereto simulation signals having a first or a second logic state, as well as testing means connected to the output of the circuit and able to mark the logic level of the output signal of said circuit. The testing means comprise a counter having an input for loading a predetermined value corresponding to the number of components to be simulated in the testing circuit, as well as another counter connected to the outputs of the generator for receiving a resetting signal and incrementation pulses. These means also comprise means for marking the logic level of the output signal of the circuit. Application to the testing of circuits having logic components.

Abstract: The invention relates to a generator of predetermined sequences of combined logic signals. This generator is characterized in that it comprises sequential means having outputs (EVEN1 . . . EVENR) supplying at each instant t.sub.i of a succession of instants of each sequence, a number q.sub.i of logic level 1 signals and a number R-q.sub.i of logic level 0 signals, the sum of the numbers q.sub.i being equal to a predetermined number p, means (CHl, VALCOL) connected to the sequential means for initializing and supplying the signal corresponding to the sequence, controlled means connected to the sequential means so that the latter supply at instants t.sub.i the q.sub.i logic level 1 signals and the R-q.sub.i logic level 0 signals, so that the sum of the numbers q.sub.i is equal to p, and stop means connected to the sequential means for stopping the supply of signals on the R outputs, following a predetermined sequence of combined signals.

Abstract: A combined logic signal generator enables combination of p output signals at logic level 1 and N-p output signals at the logic level 0 among N outputs (QP1, . . . QPN) of the generator on which the p logic signals of level 1 and N-p logic signals of level 0 are available with Np being constant. The generator utilizes an assembly (P) of N storage parts (P1, P2, . . . PN) and a device CH for introducing into the storage means P1, P2 . . . PN the logic levels of signals corresponding to a predetermined combination and a control means M to manage the storage means of the assembly P to obtain all the combinations which follow the predetermined starting combination. Lastly, the system utilizes a device A for stopping the generation of the combinations after a second predetermined combination.

Abstract: The invention relates to a system for testing the malfunctioning or correct operation of a circuit with n logic components. These components respectively present a simulation input receiving a malfunctioning or correct operation simulation signal. The system is characterized in that it comprises test means for placing each component respectively in a state of malfunctioning or of correct operation and vice versa, for one or more combinations of the components of the circuit, the test means present a characteristic output which furnishes a signal of which the logic level depends on the state of malfunctioning or of correct operation and vice versa, of each of the components of the circuit. Finally, the system comprises stop means for stopping the test means when the tests to be carried out are finished. The invention is more particularly applied to tests of electronic circuits and, by analogy, to tests of hydraulic circuits.