Patents by Inventor André-Jacques Auberton-Herve

André-Jacques Auberton-Herve has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6429104
    Abstract: The invention concerns a method for treating substrates, in particular semiconductors, by implanting atoms so as to produce a substrate of cavities at a controlled depth, characterized in that it comprises steps which consists in: implanting atoms in the substrate at a first depth, to obtain a first concentration of atoms at said first depth; implanting atoms in the substrate at a second depth, different from the first, to obtain at said second depth, a second concentration of atoms, lower than the first; carrying out on the substrate a treatment for causing at least part of the atoms implanted in said second depth to migrate towards the first depth so as to create the cavities at the first depth preferably.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: August 6, 2002
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventor: Andre-Jacques Auberton-Herve
  • Patent number: 6403450
    Abstract: The invention concerns a method for treating, a substrate comprising a semi-conducting layer (4) on at least one of its surfaces. Said method comprises a step for annealing the substrate and a step for forming, an oxide layer (6) at the semi-conducting layer (4) surface, carried out before the end of the annealing step, protecting the remainder of the semi-conducting layer (4).
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: June 11, 2002
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Christophe Maleville, Thierry Barge, Bernard Aspar, Hubert Moriceau, André-Jacques Auberton-Herve
  • Patent number: 4954989
    Abstract: A static memory cell of the metal-insulator-semiconductor type, which can be used in the microelectronics field for producing random access memories for storing binary information. This MIS type memory cell is a random access static memory cell known under the abbreviation SRAM. A bistable flip-flop is formed by a MIS transistor and a parasitic bipolar transistor. The source and drain of the MIS transistor respectively formed by constituting the emitter and collector of the bipolar transistor. The region of the channel of the MIS transistor located between the source and drain serves as the base for the bipolar transistor. The base is completely isolated from the outside of the memory cell. The gate electrode of the MIS transistor is electrically isolated from the region of the channel. There is an addressing circuit for the flip-flop for storing binary information in the form of the absence or presence of current.
    Type: Grant
    Filed: April 10, 1989
    Date of Patent: September 4, 1990
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Andre-Jacques Auberton-Herve, Benoit Giffard