Patents by Inventor André Labonté

André Labonté has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12276119
    Abstract: The present invention provides a transition moulding comprised of an elongate piece having three strips of adhesive material, a plurality of holes, and thin lateral beveled edges. The holes are for embedding adhesive or mortar as well as placing mechanical fasteners to secure the moulding to the sub floor. The adhesive bands are for securing the flooring material and the central adhesive band is for placing a clip that is configured and sized to hold a “T” separator placed between the two flooring materials. There is also a crease to facilitate the folding or breaking of the moulding for when it is used against a wall or at the end of a floor such as on door sills or staircase.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: April 15, 2025
    Inventor: Paul-André Labonté
  • Publication number: 20200098913
    Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Ruilong XIE, Chanro PARK, Andre LABONTE, Daniel CHANEMOUGAME
  • Publication number: 20180240883
    Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 23, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: DANIEL CHANEMOUGAME, ANDRE LABONTE, RUILONG XIE, LARS LIEBMANN, NIGEL CAVE, GUILLAUME BOUCHE
  • Publication number: 20180204927
    Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 19, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: DANIEL CHANEMOUGAME, ANDRE LABONTE, RUILONG XIE, LARS LIEBMANN, NIGEL CAVE, GUILLAUME BOUCHE
  • Publication number: 20180182668
    Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 28, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: RUILONG XIE, CHANRO PARK, ANDRE LABONTE, LARS LIEBMANN
  • Publication number: 20180012887
    Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 11, 2018
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Andre LABONTE, Ruilong XIE, Xunyuan ZHANG
  • Publication number: 20180012798
    Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.
    Type: Application
    Filed: August 29, 2017
    Publication date: January 11, 2018
    Applicant: GLOBALFOUDRIES Inc.
    Inventors: Andre LABONTE, Ruilong XIE, Xunyuan ZHANG
  • Publication number: 20170092764
    Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong XIE, Andre LABONTE, Andreas KNORR
  • Publication number: 20160336399
    Abstract: There is set forth herein a gate contact structure for a gate. The gate contact structure can include a first contact layer and a second contact layer. In one embodiment, a gate contact layer can define a contact that provides a gate tie down. In one embodiment, a gate contact layer can have a minimum width larger than a gate length.
    Type: Application
    Filed: May 14, 2015
    Publication date: November 17, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Andre LABONTE, Ryan Ryoung-han KIM
  • Patent number: D975131
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 10, 2023
    Assignee: GOOGLE LLC
    Inventors: Rohan Ketan Shah, Sumir Kataria, Lucas Dupin Moreira Costa, Ayad Aliomer, John Reck, Jonas Alon Naimark, John Thomas DiMartile, III, James Gundersen, André Labonté, Amanda Alexander, Chris Joel, Daniel Nizri, Anthony Robledo, Andy Stewart
  • Patent number: D985019
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: May 2, 2023
    Assignee: GOOGLE LLC
    Inventors: Rohan Ketan Shah, Sumir Kataria, Lucas Dupin Moreira Costa, Ayad Aliomer, John Reck, Jonas Alon Naimark, John Thomas DiMartile, III, James Gundersen, André Labonté, Amanda Alexander, Chris Joel, Daniel Nizri, Anthony Robledo, Andy Stewart
  • Patent number: D985580
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: May 9, 2023
    Assignee: GOOGLE LLC
    Inventors: Rohan Ketan Shah, Sumir Kataria, Lucas Dupin Moreira Costa, Ayad Aliomer, John Reck, Jonas Alon Naimark, John Thomas DiMartile, III, James Gundersen, André Labonté, Amanda Alexander, Chris Joel, Daniel Nizri, Anthony Robledo, Andy Stewart