Patents by Inventor André P. Labonté

André P. Labonté has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240295688
    Abstract: Embodiments described herein provide for methods of forming optical device structures. The methods utilize rotation of a substrate, to have the optical device structures formed thereon, and tunability of etch rates of a patterned resist disposed over the substrate and one of a device layer or the substrate to form the optical device structures without multiple lithographic patterning steps and angled etch steps.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Levent COLAK, Ludovic GODET, Andre P. LABONTE
  • Publication number: 20230021915
    Abstract: Embodiments described herein provide for methods of forming optical device structures. The methods utilize rotation of a substrate, to have the optical device structures formed thereon, and tunability of etch rates of a patterned resist disposed over the substrate and one of a device layer or the substrate to form the optical device structures without multiple lithographic patterning steps and angled etch steps.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Inventors: Levent COLAK, Ludovic GODET, Andre P. LABONTE
  • Publication number: 20200363719
    Abstract: A method for forming a device structure is disclosed. The method of forming the device structure includes forming a variable-depth structure in a device material layer using cyclic-etch process techniques. A plurality of device structures is formed in the variable-depth structure to define vertical or slanted device structures therein. The variable-depth structure and the vertical or slanted device structures are formed using an etch process.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 19, 2020
    Inventors: Andre P. LABONTE, Ludovic GODET, Rutger MEYER TIMMERMAN THIJSSEN
  • Publication number: 20200058757
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 20, 2020
    Inventors: Ruilong XIE, Chanro PARK, Julien FROUGIER, Kangguo CHENG, Andre P. LABONTE
  • Patent number: 8580628
    Abstract: An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: November 12, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: André P. Labonté, Richard S. Wise, Ying Li, Brett H. Engel
  • Patent number: 8507375
    Abstract: An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 13, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: André P. Labonté, Richard S. Wise
  • Publication number: 20130200441
    Abstract: An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: André P. Labonté, Richard S. Wise, Ying Li, Brett H. Engel
  • Publication number: 20130200471
    Abstract: An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: André P. Labonté, Richard S. Wise