Patents by Inventor Andrés Felipe AMAYA BELTRÁN

Andrés Felipe AMAYA BELTRÁN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and circuit for compensating for the offset voltage of electronic circuits
    Patent number: 10833689
    Abstract: The present invention corresponds to a method and a circuit for compensating the offset voltage of electronic circuits, where the circuit implementing the method comprises: a dynamic comparator (1); a phase detector (6) connected to the dynamic comparator (1), the phase detector (6); a finite-state machine (9) connected to the phase detector (4), a first digital-analog converter (12) connected to an output of the finite-state machine (9); a second digital-analog converter (13) connected to another output (11) of the finite-state machine (9); a polarization block (14) with a first input (15) connected to the output of the first digital-analog converter (12) and a second input (16) connected to the output of the second digital-analog converter (13); where the polarization block (14) polarizes an electronic circuit (17) and the dynamic comparator (1), the phase detector (6), and the finite-state machine (9) are connected to a clock signal (3).
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 10, 2020
    Assignee: UNIVERSIDAD INDUSTRIAL DE SANTANDER
    Inventors: Andrés Felipe Amaya Beltrán, Rodolfo Villamizar Mejía, Élkim Felipe Roa Fuentes
  • Method and Circuit for Compensating for the Offset Voltage of Electronic Circuits
    Publication number: 20200186158
    Abstract: The present invention corresponds to a method and a circuit for compensating the offset voltage of electronic circuits, where the circuit implementing the method comprises: a dynamic comparator (1); a phase detector (6) connected to the dynamic comparator (1), the phase detector (6); a finite-state machine (9) connected to the phase detector (4), a first digital-analog converter (12) connected to an output of the finite-state machine (9); a second digital-analog converter (13) connected to another output (11) of the finite-state machine (9); a polarization block (14) with a first input (15) connected to the output of the first digital-analog converter (12) and a second input (16) connected to the output of the second digital-analog converter (13); where the polarization block (14) polarizes an electronic circuit (17) and the dynamic comparator (1), the phase detector (6), and the finite-state machine (9) are connected to a clock signal (3).
    Type: Application
    Filed: June 28, 2017
    Publication date: June 11, 2020
    Applicant: Universidad Industrial de Santander
    Inventors: Andrés Felipe AMAYA BELTRÁN, Rodolfo VILLAMIZAR MEJÍA, Élkim Felipe ROA FUENTES