Abstract: An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

Abstract: An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

Abstract: A memory device for an error-correcting block code is provided, whereby each code word of the block code can have data bits and parity bits. The device also includes a memory for storing the data bits and the parity bits of each code word, and includes an error detection circuit, which is formed to detect an error of the data bits in a code word by evaluating exactly one subset of the stored parity bits of the code word. The subset being smaller than the total number of parity bits of the code word.

Abstract: A memory device for an error-correcting block code is provided, whereby each code word of the block code can have data bits and parity bits. The device also includes a memory for storing the data bits and the parity bits of each code word, and includes an error detection circuit, which is formed to detect an error of the data bits in a code word by evaluating exactly one subset of the stored parity bits of the code word. The subset being smaller than the total number of parity bits of the code word.