Patents by Inventor Andras Pozsgay
Andras Pozsgay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11356055Abstract: A photovoltaic, PV, module level monitoring, MLM, system (1) comprising a base station, BS, (2) connected by means of power cables (3) to module level devices, MLD, (4) which are provided to monitor and/or to control associated photovoltaic modules, PVMs, (5), wherein the base station, BS, (2) comprises a base station transmitter (2A) adapted to transmit Rapid Shut Down, RSD, control signals, CS, in predefined time slots, TSCS, in a downlink channel, DL-CH, through said power cables (3) to said module level devices, MLDs, (4) and a base station receiver (2B) adapted to receive monitoring signals, MS, generated by said module level devices, MLDs, (4) through said power cables (3) within time slots, TSMS, via an uplink channel, UL-CH, assigned to the module level devices, MLDs, (4).Type: GrantFiled: June 17, 2019Date of Patent: June 7, 2022Assignee: Fronius International GmbHInventors: Andras Pozsgay, Yohan Chavanel
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Publication number: 20210234507Abstract: A photovoltaic, PV, module level monitoring, MLM, system (1) comprising a base station, BS, (2) connected by means of power cables (3) to module level devices, MLD, (4) which are provided to monitor and/or to control associated photovoltaic modules, PVMs, (5), wherein the base station, BS, (2) comprises a base station transmitter (2A) adapted to transmit Rapid Shut Down, RSD, control signals, CS, in predefined time slots, TSCS, in a downlink channel, DL-CH, through said power cables (3) to said module level devices, MLDs, (4) and a base station receiver (2B) adapted to receive monitoring signals, MS, generated by said module level devices, MLDs, (4) through said power cables (3) within time slots, TSMS, via an uplink channel, UL-CH, assigned to the module level devices, MLDs, (4).Type: ApplicationFiled: June 17, 2019Publication date: July 29, 2021Inventors: Andras Pozsgay, Yohan Chavanel
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Patent number: 9379776Abstract: The invention relates to a system for low data-rate communication over a modulated direct carrier current, having one or more communication transmitters (6, 8), a communication receiver (10), and a wire bus (12) forming a shared transmission channel. Each communication transmitter (6, 8) is configured to form a first raw staggered transmission frame according to a second staggered transmission frame, said staggered transmission frames using a set of separate basic chip-encoding sequences. The basic encoding sequences or staggering the symbols used by all the communication transmitters (4, 6) are identical, and the times of the initial transmission of the second staggered frames produced by each transmitter (6, 8) are autonomously and freely determined by each transmitter (6, 8), without taking into account any synchronization signal external to the transmitter (6, 8).Type: GrantFiled: March 14, 2014Date of Patent: June 28, 2016Assignee: MERSEN France SB SASInventors: Andras Pozsgay, Armin Wellig
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Patent number: 9306082Abstract: The invention relates to a module for locally controlling a photovoltaic panel that includes: first and second terminals (B1, B2) for connecting in series by a single conductor (13) having homologous modules; a first terminal (A1) for connecting the photovoltaic panel, said first terminal being connected to the first terminal (B1) for connecting in series; a switcher (S) that is connected between the second terminal (B2) for connecting in series and a second terminal (A2) connecting the panel; a diode (D0) that is connected between the first and second terminals (B1, B2) for connecting in series; a converter (70) that is provided so as to supply power to the module on the basis of the voltage that is developed by the panel between the first and second terminals (A1, A2) connecting the panel; a sensor (R3) for measuring the current flowing within the single conductor (13); and a means (60, 62) for closing the switcher when the current flowing within the single conductor exceeds a threshold.Type: GrantFiled: January 10, 2011Date of Patent: April 5, 2016Inventor: Andras Pozsgay
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Publication number: 20160036493Abstract: The invention relates to a system for low data-rate communication over a modulated direct carrier current, having one or more communication transmitters (6, 8), a communication receiver (10), and a wire bus (12) forming a shared transmission channel. Each communication transmitter (6, 8) is configured to form a first raw staggered transmission frame according to a second staggered transmission frame, said staggered transmission frames using a set of separate basic chip-encoding sequences. The basic encoding sequences or staggering the symbols used by all the communication transmitters (4, 6) are identical, and the times of the initial transmission of the second staggered frames produced by each transmitter (6, 8) are autonomously and freely determined by each transmitter (6, 8), without taking into account any synchronization signal external to the transmitter (6, 8).Type: ApplicationFiled: March 14, 2014Publication date: February 4, 2016Applicant: MERSEN France SB SASInventors: Andras POZSGAY, Armin WELLIG
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Publication number: 20120306289Abstract: The invention relates to a module for locally controlling a photovoltaic panel that includes: first and second terminals (B1, B2) for connecting in series by a single conductor (13) having homologous modules; a first terminal (A1) for connecting the photovoltaic panel, said first terminal being connected to the first terminal (B1) for connecting in series; a switcher (S) that is connected between the second terminal (B2) for connecting in series and a second terminal (A2) connecting the panel; a diode (D0) that is connected between the first and second terminals (B1, B2) for connecting in series; a converter (70) that is provided so as to supply power to the module on the basis of the voltage that is developed by the panel between the first and second terminals (A1, A2) connecting the panel; a sensor (R3) for measuring the current flowing within the single conductor (13); and a means (60, 62) for closing the switcher when the current flowing within the single conductor exceeds a threshold.Type: ApplicationFiled: January 10, 2011Publication date: December 6, 2012Inventor: Andras Pozsgay
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Patent number: 8203475Abstract: A parallel, multi-stage noise shaping (MASH) delta-sigma (??) modulator reduces the required operating frequency by predicting the inputs to later stages of a serial MASH modulator to be multiples of the MASH input. An Nth order parallel MASH ?? modulator generates N outputs (one from each stage) in a single modulator cycle. Accordingly, the Nth order parallel MASH ?? modulator may be operated at 1/N the frequency of a corresponding prior art Nth order serial MASH ?? modulator.Type: GrantFiled: May 24, 2010Date of Patent: June 19, 2012Assignee: ST-Ericsson SAInventors: Razak Hossain, Andras Pozsgay
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Patent number: 8165549Abstract: An electronic device, includes sigma-delta modulation circuit to operate with a clock signal and having output circuitry to deliver a digital data signal. First circuitry delivers a radiofrequency transposition signal. A notch filter includes radiofrequency digital-to-analog conversion blocks, having first input circuitry coupled to the output circuitry. Second input circuitry receives the radiofrequency transposition signal. Second output circuitry delivers a radiofrequency analog signal. Digital delay circuitry is controlled by the clock signal and includes a delay block between the two first input circuits. The frequency of a notch of the notch filter is related to the value of the delay from the delay block. Summation circuitry sums the radiofrequency signals.Type: GrantFiled: September 11, 2008Date of Patent: April 24, 2012Assignees: STMicroelectronics N.V., STMicroelectronics SAInventors: Andras Pozsgay, Frédéric Paillardet
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Publication number: 20110285565Abstract: A parallel, multi-stage noise shaping (MASH) delta-sigma (??) modulator reduces the required operating frequency by predicting the inputs to later stages of a serial MASH modulator to be multiples of the MASH input. An Nth order parallel MASH ?? modulator generates N outputs (one from each stage) in a single modulator cycle. Accordingly, the Nth order parallel MASH ?? modulator may be operated at 1/N the frequency of a corresponding prior art Nth order serial MASH ?? modulator.Type: ApplicationFiled: May 24, 2010Publication date: November 24, 2011Applicant: ST-Ericsson SAInventors: Razak Hossain, Andras Pozsgay
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Patent number: 7755524Abstract: A method for processing a digital signal includes an elementary processing including a radiofrequency transposition with a radiofrequency transposition signal and a digital to analog conversion of the transposed digital signal for delivering a radiofrequency analog signal. The digital to analog conversion is controlled by a control signal and a power control signal, the control signal having a frequency twice the frequency of the radiofrequency transposition signal. Each transition of the radiofrequency transposition signal occurs between two consecutive pulses of said control signal.Type: GrantFiled: September 11, 2008Date of Patent: July 13, 2010Assignees: STMicroelectronics N.V., STMicroelectronics S.A.Inventors: Andras Pozsgay, Mounir Boulemnakher, Frédéric Paillardet
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Patent number: 7567789Abstract: The method and device include the generation of two output signals (IRF, QRF) in phase quadrature, having a frequency spectrum including a dominant harmonic at a wanted frequency FC. The generation of a periodic basic signal (VP) having a frequency FOSC equal to the product of R and the desired frequency FC is included, R being a non-integer rational number greater than one and equal to a ratio p/q, in which p is an integer multiple of 4 and q an odd integer. Also included is a processing of the basic signal including, for example, at least a preprocessing having a frequency division by p with elimination of the even harmonics and a frequency multiplication by q.Type: GrantFiled: May 10, 2006Date of Patent: July 28, 2009Assignee: STMicroelectronics N.V.Inventor: Andras Pozsgay
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Publication number: 20090082006Abstract: An electronic device, includes sigma-delta modulation circuit to operate with a clock signal and having output circuitry to deliver a digital data signal. First circuitry delivers a radiofrequency transposition signal. A notch filter includes radiofrequency digital-to-analog conversion blocks, having first input circuitry coupled to the output circuitry. Second input circuitry receives the radiofrequency transposition signal. Second output circuitry delivers a radiofrequency analog signal. Digital delay circuitry is controlled by the clock signal and includes a delay block between the two first input circuits. The frequency of a notch of the notch filter is related to the value of the delay from the delay block. Summation circuitry sums the radiofrequency signals.Type: ApplicationFiled: September 11, 2008Publication date: March 26, 2009Applicant: STMicroelectronics SAInventors: Andras Pozsgay, Frederic Paillardet
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Publication number: 20090073013Abstract: A method for processing a digital signal includes an elementary processing including a radiofrequency transposition with a radiofrequency transposition signal and a digital to analog conversion of the transposed digital signal for delivering a radiofrequency analog signal. The digital to analog conversion is controlled by a control signal and a power control signal, the control signal having a frequency twice the frequency of the radiofrequency transposition signal. Each transition of the radiofrequency transposition signal occurs between two consecutive pulses of said control signal.Type: ApplicationFiled: September 11, 2008Publication date: March 19, 2009Applicant: STMicroelectronics SAInventors: Andras Pozsgay, Mounir Boulemnakher, Frederic Paillardet
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Publication number: 20060258314Abstract: The method and device include the generation of two output signals (IRF, QRF) in phase quadrature, having a frequency spectrum including a dominant harmonic at a wanted frequency FC. The generation of a periodic basic signal (VP) having a frequency FOSC equal to the product of R and the desired frequency FC is included, R being a non-integer rational number greater than one and equal to a ratio p/q, in which p is an integer multiple of 4 and q an odd integer. Also included is a processing of the basic signal including, for example, at least a preprocessing having a frequency division by p with elimination of the even harmonics and a frequency multiplication by q.Type: ApplicationFiled: May 10, 2006Publication date: November 16, 2006Applicant: STMicroelectronics N.V.Inventor: Andras Pozsgay