Abstract: In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a first reference clock signal and generate a first reference time signal based on the timing signal and the first reference clock signal. The IC chip is configured to generate a second reference time signal based on the first reference time signal and a second reference clock signal, different from the first reference clock signal The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The IC chip is configured to synchronize one or more actions performed by the IC chip based on one or more of the first reference time signal or the second reference time signal.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a first reference clock signal and generate a first reference time signal based on the timing signal and the first reference clock signal. The IC chip is configured to generate a second reference time signal based on the first reference time signal and a second reference clock signal, different from the first reference clock signal The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The IC chip is configured to synchronize one or more actions performed by the IC chip based on one or more of the first reference time signal or the second reference time signal.

Abstract: In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal. The IC chips is configured to a reference time signal based on the timing signal and the reference clock signal. The IC chip includes a phase lock loop (PLL). The PLL is synchronized based on the reference time signal.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal. The IC chips is configured to a reference time signal based on the timing signal and the reference clock signal. The IC chip includes a phase lock loop (PLL). The PLL is synchronized based on the reference time signal.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. Each of the first, second, and third reference time signals is associated with a count of a number of cycles of the reference clock signal starting from a same particular cycle of the reference clock signal.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips include respectively first, second, and third phase lock loop (PLL). The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. The first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. Each of the first, second, and third reference time signals is associated with a count of a number of cycles of the reference clock signal starting from a same particular cycle of the reference clock signal.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Technology is described for reducing display update time for a near-eye display (NED) device. A point of focus in the NED field of view is identified, often based on natural user input data. A communication module of a computer system communicatively coupled to the NED device transmits lossless priority data, an example of which is user focal region image data, using one or more communication techniques for satisfying lossless transmission criteria. Allowed loss image data is identified based at least in part on its distance vector from a point of focus in the display field of view. An example of allowed loss image data is image data to be displayed outside the user focal region. The allowed loss image data is transmitted and extracted from received image data allowing for lossy transmission.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.