Patents by Inventor Andre Brockmeier

Andre Brockmeier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11787686
    Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 17, 2023
    Assignee: Infineon Technologies AG
    Inventors: Andre Brockmeier, Wolfgang Friza, Daniel Maurer
  • Publication number: 20230288695
    Abstract: A microelectromechanical systems (MEMS) mirror package assembly includes: a MEMS wafer including a stator portion and a rotor portion that includes a MEMS mirror configured to rotate about an axis, wherein the MEMS mirror is suspended over a back cavity, wherein the MEMS wafer defines a first portion of the back cavity; a spacer wafer, wherein the backside of the spacer wafer is bonded to the frontside of the MEMS wafer, wherein the spacer wafer defines a first portion of a front cavity arranged over the MEMS mirror; a transparent cover wafer, wherein the backside of the transparent cover wafer is bonded to the frontside of the spacer wafer, wherein the transparent cover wafer includes a transparent dome structure arranged over the MEMS mirror and defining a second portion of the front cavity. The center of the MEMS mirror is arranged substantially at a vertex of the transparent dome structure.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Applicant: Infineon Technologies AG
    Inventors: Andre BROCKMEIER, Ulf BARTL, Kurt SORSCHAG
  • Patent number: 11576259
    Abstract: A carrier configured to be attached to a semiconductor substrate via a first surface comprises a continuous carbon structure defining a first surface of the carrier, and a reinforcing material constituting at least 2 vol-% of the carrier.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 7, 2023
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Andre Brockmeier, Tobias Franz Wolfgang Hoechbauer, Gerhard Metzger-Brueckl, Matteo Piccin, Francisco Javier Santos Rodriguez
  • Patent number: 11502190
    Abstract: A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 ?m to 200 ?m. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 ?m to 5 ?m.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Andre Brockmeier, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20220293558
    Abstract: A method for forming semiconductor devices includes: attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices; forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure; and reducing a thickness of the wide band-gap semiconductor wafer after attaching the glass structure. Additional methods for forming semiconductor devices are described.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 15, 2022
    Inventors: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez, Ronny Kern
  • Patent number: 11393784
    Abstract: A method for forming semiconductor devices includes attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices. The method further includes forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez, Ronny Kern
  • Publication number: 20220085174
    Abstract: A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Inventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
  • Publication number: 20220033249
    Abstract: The semiconductor device includes a microelectromechanical system (MEMS) chip having a first main surface and a second main surface situated opposite the first main surface, a first glass-based substrate, on which the MEMS chip is arranged by its first main surface, and a second substrate, which is arranged on the second main surface of the MEMS chip, wherein the MEMS chip has a first recess connected to the surroundings by way of a plurality of perforation holes arranged in the first substrate.
    Type: Application
    Filed: July 15, 2021
    Publication date: February 3, 2022
    Applicant: Infineon Technologies AG
    Inventors: Andre BROCKMEIER, Barbara Angela GLANZER, Marten OLDSEN, Francesco SOLAZZI, Carsten VON KOBLINSKI
  • Patent number: 11211459
    Abstract: An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
  • Publication number: 20210363002
    Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Inventors: Andre Brockmeier, Wolfgang Friza, Daniel Maurer
  • Patent number: 11180362
    Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: November 23, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andre Brockmeier, Wolfgang Friza, Daniel Maurer
  • Patent number: 11148943
    Abstract: A semiconductor element is formed in a mesa portion of a semiconductor substrate. A cavity is formed in a working surface of the semiconductor substrate. The semiconductor substrate is brought in contact with a glass piece made of a glass material and having a protrusion. The glass piece and the semiconductor substrate are arranged such that the protrusion extends into the cavity. The glass piece is bonded to the semiconductor substrate. The glass piece is in-situ bonded to the semiconductor substrate by pressing the glass piece against the semiconductor substrate. During the pressing a temperature of the glass piece exceeds a glass transition temperature and the temperature and a force exerted on the glass piece are controlled to fluidify the glass material and after re-solidifying the protrusion completely fills the cavity.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez
  • Publication number: 20210309513
    Abstract: A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.
    Type: Application
    Filed: March 1, 2021
    Publication date: October 7, 2021
    Applicant: Infineon Technologies AG
    Inventors: Andre BROCKMEIER, Stephan HELBIG, Adolf KOLLER
  • Publication number: 20210253421
    Abstract: A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 19, 2021
    Inventors: Andre BROCKMEIER, Markus BERGMEISTER, Bernhard GOLLER, Daniel PIEBER, Sokratis SGOURIDIS
  • Patent number: 11046577
    Abstract: In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: June 29, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andre Brockmeier, Roland Rupp, Francisco Javier Santos Rodriguez
  • Publication number: 20210167195
    Abstract: A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 ?m to 200 ?m. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 ?m to 5 ?m.
    Type: Application
    Filed: November 20, 2020
    Publication date: June 3, 2021
    Inventors: Andre Brockmeier, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20200385264
    Abstract: In a method of generating a microelectromechanical system, MEMS, device, a MEMS substrate including a movable element is provided. A glass cover member including a glass cover is formed by hot embossing. The glass cover member is bonded to the MEMS substrate so as to hermetically seal by the glass cover a cavity in which the movable element is arranged.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 10, 2020
    Applicant: Infineon Technologies AG
    Inventors: Andre BROCKMEIER, Rafael JANSKI, Boris KIRILLOV, Marten OLDSEN, Clemens ROESSLER, Francisco Javier SANTOS RODRIGUEZ, Sokratis SGOURIDIS, Kurt SORSCHAG
  • Patent number: 10766766
    Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 8, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andre Brockmeier, Wolfgang Friza, Daniel Maurer
  • Publication number: 20200277183
    Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Andre Brockmeier, Wolfgang Friza, Daniel Maurer
  • Patent number: 10748787
    Abstract: A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Carsten von Koblinski, Ulrike Fastner, Andre Brockmeier, Peter Zorn