Abstract: A superscalar processor with a precise fault mechanism. Instructions are grouped into a cluster of instructions to be executed simultaneously by the superscalar processor. The cluster is formed from consecutively sequenced instructions according to a predetermined set of grouping rules. If at least one previously executed instruction exists, the consecutively sequenced instructions begin with an initial instruction that is the first instruction following a last previously executed instruction. Each instruction of the cluster is decoded and faulting instructions, if any, of the cluster are determined. Faulting instructions are instructions having an associated trace fault. If no faulting instructions were found, each instruction in the cluster is executed simultaneously. If, however, at least one faulting instruction was found, a break faulting instruction is determined. The break faulting instruction is the first faulting instruction in the consecutive sequence of the cluster instructions.