Patents by Inventor Andre I. Nasr

Andre I. Nasr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7470562
    Abstract: Methods of forming a field effect transistor by forming a gate electrode on a semiconductor substrate and forming aluminum oxide spacers on sidewalls of the gate electrode. Source and drain region dopants of first conductivity type are implanted into the semiconductor substrate using the aluminum oxide spacers as an implant mask. Thereafter, the aluminum oxide spacers are selectively removed by exposing them to tetramethyl ammonium hydroxide (TMAH). The step of selectively removing the aluminum oxide spacers may include exposing the aluminum oxide spacers to tetramethyl ammonium hydroxide having a temperature of about 80° C.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: December 30, 2008
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation
    Inventors: Jong Pyo Kim, Andre I. Nasr
  • Patent number: 6825545
    Abstract: A semiconductor method integrates a DTC on SOI for the purpose of accomplishing a robust circuit design with low noise while reducing the silicon area used. The DTC for SOI devices comprises a buried oxide layer on a silicon substrate with a silicon layer over the buried oxide layer. Shallow trench insulation extends to the buried oxide layer in the silicon layer. A first trench is formed in the shallow trench insulation and extends through the buried oxide layer into the silicon substrate. The first trench has formed on the walls thereof an oxide insulating layer and is then filled with polysilicon to form the DTC. A second trench is formed in the silicon layer adjacent to the first trench and extends through the buried oxide layer into the silicon substrate. The second trench is filled with polysilicon and forms the substrate contact for the DTC.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: November 30, 2004
    Assignee: International Business Machines Corporation
    Inventor: Andre I. Nasr
  • Publication number: 20040195621
    Abstract: A semiconductor method integrates a DTC on SOI for the purpose of accomplishing a robust circuit design with low noise while reducing the silicon area used. The DTC for SOI devices comprises a buried oxide layer on a silicon substrate with a silicon layer over the buried oxide layer. Shallow trench insulation extends to the buried oxide layer in the silicon layer. A first trench is formed in the shallow trench insulation and extends through the buried oxide layer into the silicon substrate. The first trench has formed on the walls thereof an oxide insulating layer and is then filled with polysilicon to form the DTC. A second trench is formed in the silicon layer adjacent to the first trench and extends through the buried oxide layer into the silicon substrate. The second trench is filled with polysilicon and forms the substrate contact for the DTC.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 7, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Andre I. Nasr
  • Patent number: 6534351
    Abstract: A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-overlapping relationship with the gate layer. This device outperforms conventional devices in terms of performance. Lower external resistance is achieved by forming a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, forming portions of the gate underneath the spacers, electrical gate control of the shallow LDD junctions is made possible. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: March 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: K. Paul Muller, Andre I. Nasr
  • Publication number: 20020173128
    Abstract: A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-overlapping relationship with the gate layer. This device outperforms conventional devices in terms of performance. Lower external resistance is achieved by forming a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, forming portions of the gate underneath the spacers, electrical gate control of the shallow LDD junctions is made possible. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance.
    Type: Application
    Filed: March 19, 2001
    Publication date: November 21, 2002
    Applicant: International Business Machines Corporation
    Inventors: K. Paul Muller, Andre I. Nasr
  • Patent number: 5563096
    Abstract: In accordance with principles of the invention, there is provided a new process for semiconductor device fabrication. The disclosed process includes forming field isolation regions on a surface of a silicon wafer, and forming gate oxide regions selectively between the field isolation regions. A gate interconnect material is deposited over the field isolation regions and gate oxide regions. A planar surface is formed on the top of the gate interconnect material. This planarization step may be accomplished by chemical mechanical polishing or some other convenient method such as a resist etch back. After planarization of the gate interconnect material, a uniform thickness photoresist is deposited on the planar surface. A gate interconnect etch pattern is formed on the planar surface using photolithography and the gate interconnect material is etched to match a gate interconnect pattern and the photoresist is removed. Sidewall spacers are provided.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: October 8, 1996
    Assignee: Digital Equipment Corporation
    Inventor: Andre I. Nasr
  • Patent number: 5494857
    Abstract: A new method for planarization of shallow trenches is presented. Shallow trenches are patterned into a semiconductor substrate that has been coated with a layer of silicon nitride. A conformal coating of oxide is deposited onto the wafer to fill the trenches. A thin layer of etch-stop silicon and a second layer of oxide are then deposited. The second layer of oxide is patterned with a filler mask using conventional photolithographic techniques and etched to the silicon etch-stop layer, leaving blocks of oxide in the depressions above the trenches and oxide spacers along the sidewalls. Chemical mechanical polishing is then used to polish the oxide back to the silicon nitride. The process offers excellent global planarity, minimal variation in silicon nitride thickness across active areas of varying size and density, and relative insensitivity to chip design.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: February 27, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Steven S. Cooperman, Andre I. Nasr
  • Patent number: 5492858
    Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: February 20, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Amitava Bose, Marion M. Garver, Andre I. Nasr, Steven S. Cooperman
  • Patent number: 5346584
    Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where trench isolation techniques are employed. The trenches and active areas on a semiconductor substrate are conformally coated with a layer of silicon oxide. A layer of patterned polysilicon then is deposited on top of the oxide and etched to create filler blocks in depressions above the trenches. Next, the polysilicon is annealed to thereby fill the trenches with an expanded oxide block. The resulting relatively planar surface then is polished back to the nitride cap, to thereby produce a high degree of planarity across all trench and active area dimensions.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: September 13, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Andre I. Nasr, Steven S. Cooperman
  • Patent number: 5266156
    Abstract: Methods of forming local interconnects and high resistor polysilicon loads are disclosed. The local interconnects are formed by depositing a layer of polysilicon over CoSi.sub.2 in partially fabricated semiconductor wafers. The polysilicon is then coated with cobalt and annealed to form a second layer of of CoSi.sub.2. The method can be expanded to form a high resistor polysilicon load by depositing and patterning an oxide layer to form contact windows before application of the polysilicon layer. Another oxide layer is deposited over the polysilicon and patterned before application of the cobalt layer to define the areas which create the resistor load.
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: November 30, 1993
    Assignee: Digital Equipment Corporation
    Inventor: Andre I. Nasr
  • Patent number: 4912061
    Abstract: A method of fabricating a SALICIDED self aligned metal oxide semiconductor device using a disposable silicon nitride spacer, metal silicide and a single implant step for the source, drain and gate regions is disclosed. The fabrication of the device is accomplished in seven major steps: First, on a substrate having an oxide layer, an undoped polysilicon layer defining the gate region is deposited. Second, an oxide layer is grown and then a silicon nitride layer is deposited. Third, the oxide and the silicon nitride layers are selectively etched, leaving the oxide and the nitride layers on the walls of the polysilicon gate region. Fourth, a cobalt layer is deposited on the wafer and processed to form cobalt silicide, after which the cobalt that did not come in contact with the silicon or the polysilicon gate region is removed. Fifth, the nitride layer on the walls of the gate region is removed. Sixth, a single ion implant step is used to form the N-channel Transistors of the device.
    Type: Grant
    Filed: April 4, 1988
    Date of Patent: March 27, 1990
    Assignee: Digital Equipment Corporation
    Inventor: Andre I. Nasr