Abstract: A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first module may propagate one or more signals to the second module. A stall-signal may be asserted in order to stall the computational pipeline if the second module is not ready to receive the one or more signals from the first module. The one or more signals propagated from the first module and the asserted stall-signal may be buffered in a stall-buffer. The asserted stall-signal may be propagated to the first module in a next cycle. The first module may be stalled in response to the first module receiving the propagated asserted stall-signal. Next, the asserted stall-signal may be propagated up the computational pipeline.

Abstract: A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first module may propagate one or more signals to the second module. A stall-signal may be asserted in order to stall the computational pipeline if the second module is not ready to receive the one or more signals from the first module. The one or more signals propagated from the first module and the asserted stall-signal may be buffered in a stall-buffer. The asserted stall-signal may be propagated to the first module in a next cycle. The first module may be stalled in response to the first module receiving the propagated asserted stall-signal. Next, the asserted stall-signal may be propagated up the computational pipeline.

Abstract: A circuit and method for optimizing efficiency in transferring a block of data having a plurality of frames of limited size from a memory element. The circuit comprises a transmit ("TX") DMA engine and a TX Segmentation engine. The TX DMA engine is responsible for accessing overhead information for the block of data within a TX data buffer from a data descriptor dedicated to that particular TX data buffer. The TX DMA engine is further responsible for reading the block of data from the memory element to be stored local thereto. The TX Segmentation engine is responsible for segmenting the block of data into a plurality of cell packets corresponding in number to the plurality of frames. Each cell packet contains in common the overhead information for the block of data to avoid the TX DMA engine re-accessing the data descriptor to obtain the same overhead information for each frame being transferred.

Abstract: A method and an apparatus for verifying a network transporter under test which is able to perform the test and produce test results by posting test packets through network transporter without requiring large amounts of memory and producing results in a short period of time. The present invention utilizes one or more FIFO (First In First Out) buffers in which plurality of components of each packet is stored just as each packet is posted to the network transporter under test. As soon as the corresponding packet is received on the other side of the network transporter, plurality of components and the receive packet are compared and a test result is produced. As soon as such comparison is performed and completed and the test results are produced, the corresponding plurality of components stored in the FIFO is discarded and the corresponding memory space used is freed up for the next packet's test information.

Abstract: A transmission data buffer and method for buffering data to be transmitted from a host computer to an asynchronous transfer mode (ATM) telecommunications network. The transmission data buffer comprises a plurality if FIFO memories, one for each channel which is established on the connection to the ATM network. A load engine loads packets of data (e.g. AAL5, AAL5-MPEG, TCP packets) into particular FIFO memories in the transmission buffer according to a load schedule queue. The data is removed from the FIFO memories by an unload engine according to entries in a bandwidth group table. The unload engine segments the data as it is removed from the FIFOs, by removing one ATM cell payload (48-bytes) at a time, and adds the ATM cell header data. The unload engine can also generate AAL5 packet CRC fields and add a control and length field to the cell data segmented from an AAL5 packet.

Abstract: A scalable packing circuit used to byte pack data transferred from a first storage element to a second storage element. The packing circuitry comprises a word packing circuit which receives data packets of a first bit width and stores them as data packets of a second bit width equivalent to the bit width of the second storage element. Concurrently, the word packing circuit eliminates invalid words included within the data packets from the first storage element. The packing circuit also includes a byte packing circuit which removes invalid bytes within the data packets of the second bit width before transferring the data to the second storage element for contiguous storage.

Abstract: A method and network interface for controlling the flow of data between a and an ATM network is provided. The network interface resides on an ATM interface and includes a state machine for each channel supported by the ATM interface. The state machine moves from state to state based on the contents of a local buffer, indications that data for the channel is ready to be transferred from the host computer to the local buffer, and the status of operations that transfer data for the channel from the host computer to the local buffer. The ATM interface includes a DMA unit and a segmentation unit that operate responsive to the states of the various state machines to avoid inefficient transfer operations.