Abstract: A dual-port memory includes an array of dynamic storage cells and a serial register having a plurality of static stages. Each stage of the serial register is arranged for receiving a data bit from a selected storage cell of the array. A plurality of bitlines is interposed between the storage cells of the array and the stages of the serial register. At one time only a single selectable bitline is arranged for interconnecting each of the columns of storage cells with each of the stages of the serial register. Each stage of the serial register includes a latch disabling circuit for selectively enabling and disabling coupling from an output of one amplifier to an input of another amplifier. By disabling such coupling, new data easily can be written into the serial register stage. A keeper circuit in each stage of the serial register reduces power consumption.

Abstract: A data processing system includes a video random access memory with a serial register having a serial register tap addressing arrangement wherein tap addresses are decoded from column address factors and are applied to data gates associated stages of the serial register accessing data from the serial register stages. A decoder responds to a code word and generates a stages select signal that controls the data gates between the serial register stages and data lines. A plurality of code word gates, interposed in the decoder inputs and responsive to a control pulse, enable the stages select signal only while the control pulse is active. By thus limiting the decoder input to pulsed code words, sequential bit interference and inadvertent bit overwriting are avoided. An equalizer circuit, connected with each data line, equalizes the potential on the data lines before the accessed data bit is applied to the selected data line.

Abstract: A dual-port memory includes an array of dynamic storage cells and a serial register having a plurality of static stages. Each stage of the serial register is arranged for receiving a data bit from a selected storage cell of the array. A plurality of bitlines is interposed between the storage cells of the array and the stages of the serial register. At one time only a single selectable bitline is arranged for interconnecting each of the columns of storage cells with each of the stages of the serial register. Each stage of the serial register includes a latch disabling circuit for selectively enabling and disabling coupling from an output of one amplifier to an input of another amplifier. By disabling such coupling, new data easily can be written into the serial register stage. A keeper circuit in each stage of the serial register reduces power consumption.

Abstract: A video random access memory includes memory cells arranged in rows and columns. The columns of memory cells are divided into first and second portions, and the cells of each row of the first portion of memory are interleaved by address with the cells of the same row of the second portion of memory. A first half of a serial register includes a plurality of storage elements that are interleaved by address with a plurality of storage elements of a second half of the serial register. Between the first and second portions of the memory cells, column leads and a multiplexer selectively couple data from either the first portion or the second portion of the columns of the memory cells to either the first half or the second half of the serial register.