Patents by Inventor Andre L. Albot
Andre L. Albot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11663312Abstract: Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.Type: GrantFiled: September 14, 2018Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Brian F. Veale, Bruce Mealey, Andre L. Albot, Nick Stilwell
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Patent number: 11061733Abstract: A digital computing system is configured to control access to an accelerator. The system includes a processor that executes an application, and an accelerator that performs a data processing operation in response to an access request output from the application. The system further includes a virtual accelerator switchboard (VAS) to determine an availability of at least one shared credit corresponding to the accelerator and assign an available shared credit to the application. The application submits a request to access the accelerator using the assigned shared credit.Type: GrantFiled: August 30, 2018Date of Patent: July 13, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian F. Veale, Bruce Mealey, Andre L. Albot, Nick Stilwell
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Patent number: 10671369Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.Type: GrantFiled: December 18, 2017Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Andre L. Albot, Vishal C. Aslot, Thomas V. Burks, III, John D. Dietel
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Patent number: 10620932Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.Type: GrantFiled: December 18, 2017Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Andre L. Albot, Vishal C. Aslot, Thomas V. Burks, III, John D. Dietel
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Publication number: 20200089865Abstract: Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.Type: ApplicationFiled: September 14, 2018Publication date: March 19, 2020Inventors: Brian F. Veale, Bruce Mealey, Andre L. Albot, Nick Stilwell
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Publication number: 20200073721Abstract: A digital computing system is configured to control access to an accelerator. The system includes a processor that executes an application, and an accelerator that performs a data processing operation in response to an access request output from the application. The system further includes a virtual accelerator switchboard (VAS) to determine an availability of at least one shared credit corresponding to the accelerator and assign an available shared credit to the application. The application submits a request to access the accelerator using the assigned shared credit.Type: ApplicationFiled: August 30, 2018Publication date: March 5, 2020Inventors: Brian F. Veale, Bruce Mealey, Andre L. Albot, Nick Stilwell
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Patent number: 10157144Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.Type: GrantFiled: January 3, 2018Date of Patent: December 18, 2018Assignee: International Business Machines CorporationInventors: Andre L. Albot, Vishal C. Aslot, Mark Rogers, Randal C. Swanberg
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Patent number: 10157145Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.Type: GrantFiled: January 4, 2018Date of Patent: December 18, 2018Assignee: International Business Machines CorporationInventors: Andre L. Albot, Vishal C. Aslot, Mark Rogers, Randal C. Swanberg
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Patent number: 9996357Abstract: Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.Type: GrantFiled: October 30, 2015Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andre L. Albot, Vishal C. Aslot, Arnold Flores, Bruce Mealey, Mark D. Rogers
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Patent number: 9971701Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.Type: GrantFiled: October 16, 2015Date of Patent: May 15, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andre L. Albot, Vishal C. Aslot, Mark D. Rogers, Randal C. Swanberg
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Publication number: 20180129610Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.Type: ApplicationFiled: January 4, 2018Publication date: May 10, 2018Inventors: Andre L. ALBOT, Vishal C. ASLOT, Mark ROGERS, Randal C. SWANBERG
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Publication number: 20180129609Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.Type: ApplicationFiled: January 3, 2018Publication date: May 10, 2018Inventors: Andre L. ALBOT, Vishal C. ASLOT, Mark ROGERS, Randal C. SWANBERG
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Publication number: 20180121193Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.Type: ApplicationFiled: December 18, 2017Publication date: May 3, 2018Inventors: Andre L. ALBOT, Vishal C. ASLOT, Thomas V. BURKS, III, John D. DIETEL
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Publication number: 20180107472Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.Type: ApplicationFiled: December 18, 2017Publication date: April 19, 2018Inventors: Andre L. ALBOT, Vishal C. ASLOT, Thomas V. BURKS, III, John D. DIETEL
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Patent number: 9898274Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.Type: GrantFiled: January 4, 2016Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andre L. Albot, Vishal C. Aslot, Thomas V. Burks, III, John D. Dietel
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Patent number: 9898417Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.Type: GrantFiled: January 4, 2016Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andre L. Albot, Vishal C. Aslot, Mark D. Rogers, Randal C. Swanberg
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Patent number: 9898277Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.Type: GrantFiled: January 11, 2017Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andre L. Albot, Vishal C. Aslot, Thomas V. Burks, III, John D. Dietel
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Patent number: 9710254Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.Type: GrantFiled: October 28, 2015Date of Patent: July 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andre L. Albot, Vishal C. Aslot, Thomas V. Burks, III, John D. Dietel
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Patent number: 9690495Abstract: Embodiments disclose techniques for emulating memory mapped I/O (MMIO) for coherent accelerators in an error state. In one embodiment, once an operating system determines that a processor is unable to access a coherent accelerator via a MMIO operation, the operating system deletes one or more page table entries associated with MMIO of one or more hardware contexts of the coherent accelerator. After deleting the page table entries, the operating system can detect a page fault associated with execution of a process by the processor. Upon determining that the page fault was caused by the process attempting to access one of the deleted page table entries while executing a MMIO operation, the operating system emulates the execution of the MMIO operation for the faulting process, giving the process the illusion that its requested MMIO operation was successful.Type: GrantFiled: November 3, 2015Date of Patent: June 27, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andre L. Albot, Vishal C. Aslot, Bruce Mealey, Nicholas Stilwell
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Publication number: 20170161054Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.Type: ApplicationFiled: January 11, 2017Publication date: June 8, 2017Inventors: Andre L. ALBOT, Vishal C. ASLOT, Thomas V. BURKS, III, John D. DIETEL