Abstract: A processing system is disclosed. The system comprises: a processing unit; a memory adapted to store firmware code and application code for execution by the processor; and a memory access control unit adapted to control access of the processing unit to firmware code and application code stored in the memory. The memory access control unit is adapted to disable access to firmware code when access to application code is enabled, and to disable access to application code when access to firmware code is enabled.

Abstract: A processing system is disclosed. The system comprises: a processing unit; a memory adapted to store firmware code and application code for execution by the processor; and a memory access control unit adapted to control access of the processing unit to firmware code and application code stored in the memory. The memory access control unit is adapted to disable access to firmware code when access to application code is enabled, and to disable access to application code when access to firmware code is enabled.

Abstract: A method of and system for determining a number of pixels out of a plurality of pixels, which plurality of pixels forms an image strip, each pixel of the plurality of pixels having a specific colour component value is provided. The method involves determining a value of a first colour component of each pixel of the plurality of pixels, wherein the value corresponds to a first colour depth describable by a first number of bits, and binning the plurality of pixels into a second number of bins of a first histogram, wherein the second number is lower than a maximum value represented by the first number of bits, determining the number of entries in each bin of the first histogram and determining for each bin of the first histogram an average colour value of a second colour component of the pixels binned into the respective bin.

Abstract: An integrated circuit (100) is disclosed that comprises a plurality of data processing stages (110) and a data communication network comprising a plurality of data communication paths between the data processing stages (110). Each data processing stage (110) comprises a hardware layer (160) for processing data received through a data communication path and a software layer (120) arranged to communicate with the software layers of selected other data processing stages for controlling the synchronization of the data communication between the data processing stage (110) and the selected other data processing stages in response to dynamically assigned communication relationships between data processing stage (110) and the respective selected other data processing stages.