Abstract: A multilevel thermoelectric cooling (TEC) stack channels thermal power away from an element to be cooled which is mounted on a substrate such as a circuit board and may generate an intrinsic heat load. The TEC stack has an inner TEC level which is in direct or indirect thermal contact with the element and an outer TEC level. At least one of the TEC levels includes a shaped thermal guard ring which is in thermal contact with the substrate. The thermal guard ring(s) define isothermal boundaries on the substrate, and effectively channel, or “wick”, thermal power away from the element to be cooled.

Abstract: Methods and systems and systems provide for temperature control between thermoelectric coolers (TECs or TEMs) in a stack of multiple TECs, by optimizing the power suppled to each TEC in the stack. The temperatures may be continuously monitored, to continuously provide for the aforementioned power optimization.