Patents by Inventor Andre Nacul

Andre Nacul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7886283
    Abstract: An alternative to a real time operating system (RTOS) is provided based on serializing compilers. A serializing compiler can transform a multitasking application into an equivalent and optimized monolithic sequential code, to be compiled with the embedded processor's native optimizing compiler, effectively filling the RTOS gap. The serializing compiler can analyze the tasks at compile time and generate a fine-tuned, application specific infrastructure to support multitasking, resulting in a more efficient executable than one that is intended to run on top of a generic RTOS. By having control over the application execution and context switches, the serializing compiler enables the fine grain control of task timing while enhancing overall performance. The serializing compiler technology strengthens existing compilers, making them timing and task-aware.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: February 8, 2011
    Assignee: The Regents of the University of California
    Inventors: Andre Nacul, Tony Givargis
  • Publication number: 20060112377
    Abstract: The invention includes a computer and a method of operating a computer to generate a program for an embedded processor comprising the steps of compiling a multitask application with a generic front-end compiler to generate a basic block (BB) control flow graph (CFG) of the multitask application; generating non-preemptive blocks of code from the control flow graph (CFG) with a partitioning module, which blocks of code are defined as AEBs (atomic execution blocks); performing a live variable analysis on the AEB graphs to generate a live variable result; feeding back to the live variable result to the partitioning module to refine the partitions until acceptable preemption, timing, and latency are achieved, the AEB graphs having determined AEB nodes; and generating a corresponding executable code for each AEB node in a code generator.
    Type: Application
    Filed: September 14, 2005
    Publication date: May 25, 2006
    Inventors: Andre Nacul, Tony Glvargis