Abstract: A decoder circuit, for example a dual-rail decoder, receives input signals (43) from the end of a communications bus (not shown). The parity is calculated over the data wires (Do, D1, D2, D3) using exclusive OR gates (45, 47, and 49). The calculated data parity signal (51) is compared with a transmitted parity signal (53) (shown as “carry”) in an exclusive OR gate (55). Rather than connecting the control signal (57) from the exclusive OR gate (55) directly to the multiplexers (590, 591, 592, 593), the control signal (57) is instead connected to a gating circuit (71). The gating circuit (71), for example a AND gate, receives the control signal (57) as a first input signal. The gating circuit (71) also receives a second input signal in the form of a gating control signal (73). The gating control signal (73) is delayed by a predetermined amount, for example corresponding to the worst case delay of the signals in the input data signals (43).

Abstract: The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix (100) in which processors (103) are arranged in rows (101) and columns (102). Furthermore, the device (100) comprises first and second external data ports (107, 108). The rows (101) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors (103) have a first processor data port (104), which is connected with one of the first external data ports (107) by means of first essentially straight connection. The processors (103) further comprise a second processor data port (105), which is connected with one of the second external data ports (108) by means of an essentially straight second connection (110). The first connection (107) and the second connection (108) are oriented substantially orthogonal to each other.

Abstract: An electronic device has a data communication bus (200) mounted on a semiconductor substrate (120). The data communication bus (200) has a first conductor (102), a second conductor (104), a third conductor (106) and a fourth conductor (108). The conductors have been reordered and the distances (I1, I2, I3) between two neighboring conductors have been recalculated on the basis of the correlation between the data-bits conveyed by the conductors of the data communication bus (200), e.g. the number of times that the two transitions on two conductors have a predetermined value out of the total number of transitions on that conductor pair. Consequently, a data communication bus (200) is obtained in which the power consumption resulting from the charging of the cross-coupling capacitance between two neighboring conductors is reduced.

Abstract: The electronic device (10) has a data communication bus (12) consisting of a plurality of substantially parallel conductors (12a, 12b, 12c, 12d). A control circuit (14) controls the values driven onto the conductors (12a, 12b, 12c, 12d). Transition dependent delay elements (16a, 16b, 16c, 16d) are coupled between the control circuit (14) and the respective conductors (12a, 12b, 12c, 12d) to delay certain transitions on the data communication bus 12. In particular, one of the opposite transitions on neighboring conductors e.g. a first conductor (12a) and a second conductor (12b) is delayed, thus reducing the power required to charge the mutual capacitance between the first conductor (12a) and the second conductor (12b). Consequently, a data communication bus (12) with reduced power consumption is obtained.