Abstract: Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the structure with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the first silicon-containing material.

Abstract: Embodiments described herein provide for methods of forming optical device structures. The methods utilize rotation of a substrate, to have the optical device structures formed thereon, and tunability of etch rates of a patterned resist disposed over the substrate and one of a device layer or the substrate to form the optical device structures without multiple lithographic patterning steps and angled etch steps.

Abstract: Embodiments described herein provide for methods of forming optical device structures. The methods utilize rotation of a substrate, to have the optical device structures formed thereon, and tunability of etch rates of a patterned resist disposed over the substrate and one of a device layer or the substrate to form the optical device structures without multiple lithographic patterning steps and angled etch steps.

Abstract: Horizontal gate-all-around devices and methods of manufacture are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by forming a tensile film on the cladding layer. The strained tensile film results in a uniform SiGe channel.

Abstract: Embodiments described herein provide for methods of forming optical device structures. The methods utilize rotation of a substrate, to have the optical device structures formed thereon, and tunability of etch rates of a patterned resist disposed over the substrate and one of a device layer or the substrate to form the optical device structures without multiple lithographic patterning steps and angled etch steps.

Abstract: Embodiments described herein provide for methods of forming optical device structures. The methods utilize rotation of a substrate, to have the optical device structures formed thereon, and tunability of etch rates of a patterned resist disposed over the substrate and one of a device layer or the substrate to form the optical device structures without multiple lithographic patterning steps and angled etch steps.

Abstract: Embodiments described herein provide for methods of forming optical device structures. The methods utilize rotation of a substrate, to have the optical device structures formed thereon, and tunability of etch rates of a patterned resist disposed over the substrate and one of a device layer or the substrate to form the optical device structures without multiple lithographic patterning steps and angled etch steps.

Abstract: A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line.

Abstract: Embodiments described herein provide for methods of forming optical device structures. The methods utilize rotation of a substrate, to have the optical device structures formed thereon, and tunability of etch rates of a patterned resist disposed over the substrate and one of a device layer or the substrate to form the optical device structures without multiple lithographic patterning steps and angled etch steps.

Abstract: A method for forming a device structure is disclosed. The method of forming the device structure includes forming a variable-depth structure in a device material layer using cyclic-etch process techniques. A plurality of device structures is formed in the variable-depth structure to define vertical or slanted device structures therein. The variable-depth structure and the vertical or slanted device structures are formed using an etch process.

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

Abstract: A method for forming a device structure is disclosed. The method of forming the device structure includes forming a variable-depth structure in a device material layer using cyclic-etch process techniques. A plurality of device structures is formed in the variable-depth structure to define vertical or slanted device structures therein. The variable-depth structure and the vertical or slanted device structures are formed using an etch process.

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

Abstract: Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes forming a first transistor and a second transistor over a substrate. The first transistor includes a first gate structure having a first gate spacer, and the second transistor includes a second gate structure having a second gate spacer. A top portion of the first gate spacer is replaced with a first sacrificial gate spacer region, and a top portion of the second gate spacer is replaced with a second sacrificial gate spacer region. A source or drain (S/D) conductive plug trench and a S/D cap trench are formed in the dielectric region of the IC and positioned over a S/D region of the first transistor. A volume of the S/D cap trench is increased by removing the first sacrificial gate spacer region and/or the second sacrificial gate spacer region.

Abstract: Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes forming a first transistor and a second transistor over a substrate. The first transistor includes a first gate structure having a first gate spacer, and the second transistor includes a second gate structure having a second gate spacer. A top portion of the first gate spacer is replaced with a first sacrificial gate spacer region, and a top portion of the second gate spacer is replaced with a second sacrificial gate spacer region. A source or drain (S/D) conductive plug trench and a S/D cap trench are formed in the dielectric region of the IC and positioned over a S/D region of the first transistor. A volume of the S/D cap trench is increased by removing the first sacrificial gate spacer region and/or the second sacrificial gate spacer region.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.

Abstract: A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line.

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.