Abstract: A data processing system includes a shared random-access memory which is shared between a first and second asynchronous processor, wherein an access to the memory is clocked by a clock signal issuing from a first processor. A two-state selection signal is generated having a frequency equal to half the frequency of the clock signal. Access to the memory by the first processor to the memory is enabled when the selection signal is in a first state, and access to the memory by the second processor to the memory is enabled when the selection signal is in a second state. Thus, a memory is shared between two processors of different speeds, the clock signal therefore issuing from the faster processor.

Abstract: The invention concerns the overflow test circuit of an arithmetic and logic unit. The circuit described does not require receiving an indication on the operating in addition or subtraction of the ALU; it receives simply the carrying input the carrying and the result output of the cell of the highest rank of the ALU: and it supplies a positive overflow signal or a negative overflow signal, when the result of the addition or subtraction of two numbers exceeds the capacity of the ALU. Two gates with three inputs and three inverters are sufficient to establish the overflow test circuit.