Abstract: A method for estimating a time offset of a transmitted signal which comprises pilot symbols and data symbols, the method comprising: receiving the transmitted signal to produce a received signal; and processing an optimising function of the received signal at a finite number of possible time offsets to produce an estimator of the time offset.

Abstract: A least squares estimator of carrier phase and amplitude in a receiver in a communication system using a phase shift keying modulation scheme that uses both known pilot symbols and unknown data symbols is described. That is, the method exploits knowledge of pilot symbols in addition to the unknown data symbols to estimate carrier phase and amplitude. Further, an efficient recursion based estimation method is described that only requires O(L. log L) arithmetic operations where L is the number of received signals. This method uses the M-Ary rounded phase offsets to sort the data symbols and this sorted order is used to recursively calculate candidate values in an optimisation process. Simulation results show that the estimation methods Using data and pilot symbols outperform estimation methods using only data symbols (ie non-coherent detection methods). Further, the system can be used for systems using multiple M-ary phase shift keying digital modulation schemes.

Abstract: A communication system is disclosed. In an embodiment, the communication system includes a user node for receiving data from a remote application program, the data including message data for communication to a central application program operatively associated with the remote application program; plurality of geographically distributed gateway nodes; one or more access nodes for receiving the message data from the user node via a first communications interface, and communicating the message data via a second communications interface to one or more of the plurality of geographically distributed gateway nodes; and a hub for communicating with the one or more of the plurality of geographically distributed gateway nodes to receive the message data for communication to the central application.

Abstract: Parallel analog to digital converted (ADC) architectures that can be used to replace single path ADC architectures. The parallel ADC architecture can comprise N branches and one ADC per branch. These ADCs can be identical. However each branch can have a different path adjustments applied to the ADC. The path adjustments can be biases and/or gains and each ADC receives a different combination of biases and/or gain to generate multiple adjusted input signals. These are then combined to generate a quantised output signal. Using these parallel architectures a range of weighting and offset combining schemes can be employed to achieve improvements in signal to noise ratio and to reduce the impact of clipping as compared to a single path ADC architecture.