Abstract: A rheology modifier copolymer of formula (I) wherein A is a polyacidic vinyl monomer selected from maleic, fumaric, itaconic, citraconic and acid combinations thereof and anhydrides and salts thereof, B is an acrylic or methacrylic acid or salt thereof; C is a C1-C8 ester of (meth)acrylic acid; D is an associative monomer; and optionally E is a crosslinking monomer.

Abstract: A device for radar applications includes a computing engine, a radar acquisition unit connected to the computing engine, a timer unit connected to the computing engine, a cascade input port, and a cascade output port. The cascade input port is configured to convey an input signal to the computing engine and the cascade output port is configured to convey an output signal from the computing engine. Further, an according system, a radar system, a vehicle with such radar system and a method are provided.

Abstract: An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities.

Abstract: An Error signal handling comprises a circuitry configured to receive an error signal from an external device indicating an error condition in the external device. The circuitry is further configured to receive a recovery signal indicating a mitigation of the error condition in the external device or indicating that a mitigation of the error condition in the external device is possible. Furthermore, the circuitry is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the circuitry does not receive the recovery signal and otherwise to omit outputting the error condition signal.

Abstract: An error signal handling unit includes an error handler configured to receive an error signal indicating an error condition. The error handler is further configured to receive a recovery signal indicating a mitigation of the error condition or indicating that a mitigation of the error condition is possible. Furthermore, the error handler is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the error handler does not receive the recovery signal, and otherwise omit outputting the error condition signal.

Abstract: An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes.

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Abstract: An Error signal handling comprises a circuitry configured to receive an error signal from an external device indicating an error condition in the external device. The circuitry is further configured to receive a recovery signal indicating a mitigation of the error condition in the external device or indicating that a mitigation of the error condition in the external device is possible. Furthermore, the circuitry is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the circuitry does not receive the recovery signal and otherwise to omit outputting the error condition signal.

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract: A power converter system (100) comprises a power converter (102), an analyzing circuit (114) and a power converter controller (110). The power converter (102) receives a mains voltage (108) and provides power (104) to a signal processing circuit (106). The power converter (102) is configured for operating in either a first mode wherein the power converter (102) is able to supply a first power level, or in a second mode wherein the power converter (102) is able to supply a second power level. The second power level exceeds the first power level. The signal processing circuit (106) processes a signal (116) in a normal operational mode. The analyzing circuit (114) anlyzes the signal (116). The analyzing circuit (114) generates a power signal (112) that indicates a power consumption of the signal processing circuit (106) in normal operation. The power converter controller (110) receives the power signal (112) and controls the power converter (102) to operate in the first mode or in the second mode.

Abstract: An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes.

Abstract: An annulus spacer for a fuel channel assembly of a nuclear reactor. The fuel channel assembly includes a calandria tube and a pressure tube positioned at least partially within the calandria tube. The annulus spacer includes a garter spring configured to surround a portion of the pressure tube to maintain a gap between the calandria tube and the pressure tube. The garter spring includes a first end and a second end. The annulus spacer also includes a connector coupled to the first end and the second end of the garter spring. The connector allows movement of the annulus spacer when the pressure tube moves relative to the calandria tube during thermal cycles of the fuel channel assembly. The annulus spacer further includes a girdle wire positioned substantially within the garter spring and configured to form a loop around the pressure tube.

Abstract: An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities.

Abstract: The invention provides nucleic acids, and variants and fragments thereof, obtained from strains of Bacillus thuringiensis encoding polypeptides having pesticidal activity against insect pests, including Coleoptera. Particular embodiments of the invention provide isolated nucleic acids encoding pesticidal proteins, pesticidal compositions, DNA constructs, and transformed microorganisms and plants comprising a nucleic acid of the embodiments. These compositions find use in methods for controlling pests, especially plant pests.

Abstract: The invention provides nucleic acids, and variants and fragments thereof, obtained from strains of Bacillus thuringiensis encoding polypeptides having pesticidal activity against insect pests, including Lepidoptera. Particular embodiments of the invention provide isolated nucleic acids encoding pesticidal proteins, pesticidal compositions, DNA constructs, and transformed microorganisms and plants comprising a nucleic acid of the embodiments. These compositions find use in methods for controlling pests, especially plant pests.

Abstract: The invention provides nucleic acids, and variants and fragments thereof, obtained from strains of Bacillus thuringiensis encoding polypeptides having pesticidal activity against insect pests, including Coleoptera. Particular embodiments of the invention provide isolated nucleic acids encoding pesticidal proteins, pesticidal compositions, DNA constructs, and transformed microorganisms and plants comprising a nucleic acid of the embodiments. These compositions find use in methods for controlling pests, especially plant pests.

Abstract: The invention provides nucleic acids, and variants and fragments thereof, obtained from strains of Bacillus thuringiensis encoding polypeptides having pesticidal activity against insect pests, including Lepidoptera. Particular embodiments of the invention provide isolated nucleic acids encoding pesticidal proteins, pesticidal compositions, DNA constructs, and transformed microorganisms and plants comprising a nucleic acid of the embodiments. These compositions find use in methods for controlling pests, especially plant pests.

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract: An antiperspirant composition comprising a carrier substance and a water-soluble or water-dispersible thiolated polymer.