Patents by Inventor Andre Rohe
Andre Rohe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8732240Abstract: A system and method for generating a stream of content includes a content stream module that generates a model based on user input and/or prior activities using heterogeneous data sources. The heterogeneous data sources include search, entertainment, social activity and activity on third-party sites. The content stream module retrieves candidate content items that have interests that are similar to the user. The candidate content items are compared to the model and scored based upon interestingness of the content item to the user. The content stream module generates the stream of content from the candidate content items.Type: GrantFiled: April 29, 2011Date of Patent: May 20, 2014Assignee: Google Inc.Inventors: Andrew Tomkins, Dandapani Sivakumar, Sangsoo Sung, Justin Kosslyn, Todd Jackson, Andre Rohe, Ya Luo, Andrew Bunner, Sasha Sobol, Luca de Alfaro
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Patent number: 8719347Abstract: A system and method for generating a stream of content includes a content stream module that generates a model based on user input and/or prior activities using heterogeneous data sources. The heterogeneous data sources include search, entertainment, social activity and activity on third-party sites. The content stream module retrieves candidate content items that have interests that are similar to the user. The candidate content items are compared to the model and scored based upon interestingness of the content item to the user. The content stream module generates the stream of content from the candidate content items.Type: GrantFiled: September 14, 2012Date of Patent: May 6, 2014Assignee: Google Inc.Inventors: Andrew Tomkins, Dandapani Sivakumar, Sangsoo Sung, Justin Kosslyn, Todd Jackson, Andre Rohe, Ya Luo, Andrew Bunner, Sasha Sobol, Luca de Alfaro
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Patent number: 8683410Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.Type: GrantFiled: December 10, 2010Date of Patent: March 25, 2014Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Patent number: 8664974Abstract: A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.Type: GrantFiled: January 21, 2011Date of Patent: March 4, 2014Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Patent number: 8645890Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.Type: GrantFiled: September 15, 2012Date of Patent: February 4, 2014Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Publication number: 20130298000Abstract: The subject matter of this specification can be implemented in, among other things, a method for providing socially relevant content in a news domain. The methods includes a steop for receiving a request from a user for a news aggregator page related to a news story. The method also includes a step for retrieving social contents items related to the news story. The method also includes a step for providing the news aggregator page for display, wherein the news aggregator page includes multiple links to news content items related to the news story, and the retrieved social content items related to the news story.Type: ApplicationFiled: February 6, 2013Publication date: November 7, 2013Inventors: Scott ZUCCARINO, Justin Lewis Kosslyn, Richard Gingras, Andre Rohe, Vikas Sukla, Erich Schmidt, Lucian Florin Cionca, Trevor Pering, Michael Leotta
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Publication number: 20130135009Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.Type: ApplicationFiled: September 15, 2012Publication date: May 30, 2013Inventors: Andre Rohe, Steven Teig
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Patent number: 8415973Abstract: Some embodiments of the invention provide an integrated circuit (“IC”) that includes numerous configurable nodes arranged in an array having several rows and columns. In some embodiments, the configurable nodes include a first group of configurable aligned along a particular direction and a second group of configurable nodes aligned along a different direction. The IC also includes a set of direct offset turn connections arranged across the node array in a repetitive nested architecture. Each direct offset turn connection connects a node from the first group of configurable nodes to a node from the second group of configurable nodes. Each direct offset turn connection includes at least two wire segments that are arranged in at least two different directions and intersect to define a turn. No direct offset turn connection overlaps with another direct offset turn connection.Type: GrantFiled: July 22, 2011Date of Patent: April 9, 2013Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Patent number: 8281273Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.Type: GrantFiled: November 30, 2010Date of Patent: October 2, 2012Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Publication number: 20120062278Abstract: Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC's wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g.Type: ApplicationFiled: July 22, 2011Publication date: March 15, 2012Inventors: Andre Rohe, Steven Teig
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Patent number: 7994817Abstract: Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC's wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g.Type: GrantFiled: May 3, 2010Date of Patent: August 9, 2011Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Publication number: 20110181317Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.Type: ApplicationFiled: January 21, 2011Publication date: July 28, 2011Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Publication number: 20110163781Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.Type: ApplicationFiled: November 30, 2010Publication date: July 7, 2011Inventors: Andre Rohe, Steven Teig
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Publication number: 20110145776Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.Type: ApplicationFiled: December 10, 2010Publication date: June 16, 2011Inventors: Andre Rohe, Steven Teig
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Patent number: 7898291Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.Type: GrantFiled: August 3, 2009Date of Patent: March 1, 2011Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Patent number: 7870529Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.Type: GrantFiled: August 18, 2008Date of Patent: January 11, 2011Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Patent number: 7870530Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.Type: GrantFiled: August 18, 2008Date of Patent: January 11, 2011Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Patent number: 7849434Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.Type: GrantFiled: September 9, 2007Date of Patent: December 7, 2010Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Publication number: 20100210077Abstract: Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC's wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g.Type: ApplicationFiled: May 3, 2010Publication date: August 19, 2010Inventors: Andre Rohe, Steven Teig
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Patent number: 7737722Abstract: Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC's wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g.Type: GrantFiled: November 26, 2007Date of Patent: June 15, 2010Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig