Patents by Inventor Andre Schaefér
Andre Schaefér has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10079489Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.Type: GrantFiled: July 11, 2016Date of Patent: September 18, 2018Assignee: Intel CorporationInventors: Guido Droege, Andre Schaefer, Uwe Zillmann
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Publication number: 20180195619Abstract: Rotary joints are disclosed, such as for supplying liquid to a pressure chamber that is disposed between a rotatable component and a stationary component. The rotary joint may include a seal carrier having at least one channel for a fluid connection to the pressure chamber. At least two axially spaced apart sealing rings may be disposed on the seal carrier for a static sealing of the at least one channel. At least one sealing element may be non-rotatably disposed on the seal carrier and configured to form an axial and a radial seal of the pressure chamber. The at least one sealing element may be configured to bear on a ring element that is non-rotatably connected to the rotatable component when pressure is built up in the pressure chamber and the at least one sealing element may have means for reducing the axial pressure exerted on the ring element.Type: ApplicationFiled: July 1, 2016Publication date: July 12, 2018Applicants: Schaeffler Technologies AG & Co. KG, GAPI Technische Produkte GmbHInventors: Robert Heuberger, Horst Brehm, Sebastian Niederle, Marc-André Schäfer, Andre Hofmann, Andreas Flint
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Publication number: 20180122779Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: ApplicationFiled: September 8, 2017Publication date: May 3, 2018Inventors: Pete D. VOGT, Andre SCHAEFER, Warren MORROW, John B. HALBERT, Jin KIM, Kenneth D. SHOEMAKER
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Patent number: 9921640Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate.Type: GrantFiled: September 28, 2012Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Uwe Zillmann, Andre Schaefer, Ruchir Saraswat, Telesphor Kamgaing, Paul B. Fischer, Guido Droege
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Patent number: 9911689Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).Type: GrantFiled: December 23, 2013Date of Patent: March 6, 2018Assignee: INTEL CORPORATIONInventors: Kevin J. Lee, Ruchir Saraswat, Uwe Zillmann, Nicholas P. Cowley, Andre Schaefer, Rinkle Jain, Guido Droege
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Patent number: 9768148Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: GrantFiled: December 31, 2014Date of Patent: September 19, 2017Assignee: INTEL CORPORATIONInventors: Pete Vogt, Andre Schaefer, Warren Morrow, John Halbert, Jin Kim, Kenneth Shoemaker
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Publication number: 20170040255Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).Type: ApplicationFiled: December 23, 2013Publication date: February 9, 2017Applicant: INTEL CORPORATIONInventors: KEVIN J. LEE, RUCHIR SARASWAT, UWE ZILLMANN, NICHOLAS P. COWLEY, ANDRE SCHAEFER, RINKLE JAIN, GUIDO DROEGE
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Publication number: 20170011779Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.Type: ApplicationFiled: July 11, 2016Publication date: January 12, 2017Inventors: Guido Droege, Andre Schaefer, Uwe Zillmann
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Publication number: 20160306566Abstract: Embodiments including systems, methods, and apparatuses associated with reordering data retrieved from a dynamic random access memory (DRAM). A memory controller may be configured to receive an instruction from a central processing unit (CPU) and, based on the instruction, retrieve a sequential data from a DRAM. The memory controller may then be configured to reorder the sequential data and place the reordered data in one or more locations of a vector register file.Type: ApplicationFiled: December 26, 2013Publication date: October 20, 2016Inventors: Shih-Lien L. Lu, Chun Shiah, Bordoou Rong, Andre Schaefer
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Patent number: 9472249Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: GrantFiled: August 18, 2015Date of Patent: October 18, 2016Assignee: INTEL CORPORATIONInventors: Andre Schaefer, Jen-Chieh Yeh, Pei-Wen Luo
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Patent number: 9391453Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.Type: GrantFiled: June 26, 2013Date of Patent: July 12, 2016Assignee: Intel CorporationInventors: Guido Droege, Andre Schaefer, Uwe Zillmann
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Patent number: 9361970Abstract: Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.Type: GrantFiled: July 9, 2014Date of Patent: June 7, 2016Assignee: Intel CorporationInventors: Andre Schaefer, John B. Halbert
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Patent number: 9311983Abstract: A refresh voltage control engine selectively applies different high voltages to use in refresh operations. The control engine can detect that a portion of a memory device needs to be refreshed, and determine that the refresh cycle time is too short for a state of the portion of the memory device. The memory device typically has an associated refresh cycle time or time between refreshes based on the device and system architecture. The control engine can generate one or more control signals to cause the system to apply an overcharge refresh to overcharge the portion of the memory device with a refresh operation to extend the refresh cycle time for the portion of the memory device.Type: GrantFiled: June 30, 2014Date of Patent: April 12, 2016Assignee: Intel CorporationInventor: Andre Schaefer
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Patent number: 9287196Abstract: Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.Type: GrantFiled: December 28, 2012Date of Patent: March 15, 2016Assignee: Intel CorporationInventors: Ruchir Saraswat, Uwe Zillmann, Andre Schaefer, Tor Lund-Larsen
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Patent number: 9263422Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.Type: GrantFiled: January 16, 2015Date of Patent: February 16, 2016Assignee: Intel CorporationInventors: Guido Droege, Niklas Linkewitsch, Andre Schaefer
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Patent number: 9229466Abstract: A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies.Type: GrantFiled: December 31, 2011Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Ruchir Saraswat, Andre Schaefer, Uwe Zillman, Andreas Duevel, Valluri Rao, Telesphor Kamgaing, Harish Krishnamurthy
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Patent number: 9230614Abstract: Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.Type: GrantFiled: December 23, 2011Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Andre Schaefer, Ruchir Saraswat
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Publication number: 20150380072Abstract: A refresh voltage control engine selectively applies different high voltages to use in refresh operations. The control engine can detect that a portion of a memory device needs to be refreshed, and determine that the refresh cycle time is too short for a state of the portion of the memory device. The memory device typically has an associated refresh cycle time or time between refreshes based on the device and system architecture. The control engine can generate one or more control signals to cause the system to apply an overcharge refresh to overcharge the portion of the memory device with a refresh operation to extend the refresh cycle time for the portion of the memory device.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventor: ANDRE SCHAEFER
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Publication number: 20150357011Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Applicant: INTEL CORPORATIONInventors: ANDRE SCHAEFER, JEN-CHIEH YEH, PEI-WEN LUO
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Publication number: 20150317228Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.Type: ApplicationFiled: June 15, 2015Publication date: November 5, 2015Applicant: INTEL CORPORATIONInventors: Tsun Ho LIU, Andre Schaefer, Hoi M. Ng, Guy R. Murray, Oleg Mikulchenko, Xiaofang Gao