Abstract: A memory component comprises a memory cell array, signal inputs, input amplifiers connected to respective ones of the signal inputs, for receiving, amplifying and outputting data, address or control signals, a data, address or control signal generator for the memory cell array, a first supply network for supplying power to the input amplifiers and a second supply network for supplying power to the data, address or control signal generator, wherein the first supply network and the second supply network do not have a direct connection.

Abstract: Input circuit and method for setting a termination voltage. One embodiment provides a method for setting a termination voltage of an input circuit of an integrated circuit, the input circuit having an input terminal for receiving a signal, the termination voltage being applied to the input terminal, the received signal being driven with respect to the termination voltage and being evaluated by a comparison with a reference potential, the termination voltage being generated and being set in accordance with a control signal, the control signal being generated in a manner dependent on a comparison of one or more signal levels of the received signal with an assessment potential, the termination voltage being set by means of the control signal in such a way that the reliability of the signal reception is maximized.

Abstract: An input circuit for receiving a signal at an input on an integrated circuit, particularly a DRAM circuit, and for assessing the signal with respect to a reference voltage is provided. One embodiment provides a termination circuit for setting a termination voltage, wherein the termination circuit includes a first resistor and a second resistor connected in series between a high voltage potential and a low voltage potential, the termination voltage being tapped between the first and second resistors, a first voltage-dependent resistor element having a first resistance gradient connected in parallel with the first resistor and a second voltage-dependent resistor element having a second resistance gradient connected in parallel with the second resistor, wherein the resistance values of the first and second resistor elements are controlled by a control voltage to set the termination voltage.

Abstract: A memory device has a memory module, a controller, a data bus for connecting the controller and the memory module, a read clock generator, and a read clock bus for connecting the read clock generator, the memory module, and the Controller. The data bus read data from the memory module or writes data into the memory module. The read clock generator is disposed in the memory module, so that the data bus and the read clock bus are substantially symmetric, and generate a read clock for transferring data from the memory module to the controller. The data bus and the read clock bus are configured with respect to each other such that substantially no time delay between read data on the data bus and the read clock on the read clock bus exists at the controller.

Abstract: A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.

Abstract: An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.

Abstract: A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level converters generate a rising or falling edge with a different gradient. The output signals of the level converters are combined in a logic combination element. The logic combination element drives a togglable storage element, which provides the level-converted output signal. The duty ratio of the input signal is not changed during the level conversion, independently of production-dictated variations in the component parameters.

Abstract: An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.

Abstract: The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is integrated between a start time and an end time that are specified by a control signal. An integration period between the start time and the end time depends on the frequency of the data signal. The data item is assigned a logic data value based on the result of the integration. The input circuit has a comparator device, an integration device and a switching device. The data signal is first integrated in order to obtain an integration value. The comparator device compares the integration value with a prescribed threshold value. A logic data value is assigned to the data item based on the result of the comparison.

Abstract: A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level converters generate a rising or falling edge with a different gradient. The output signals of the level converters are combined in a logic combination element. The logic combination element drives a togglable storage element, which provides the level-converted output signal. The duty ratio of the input signal is not changed during the level conversion, independently of production-dictated variations in the component parameters.

Abstract: A memory device comprises a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.

Abstract: A memory device comprises a memory module, a controller, a data bus, means for providing a read clock and a read clock bus. Means for providing a read clock is arranged in the memory module, so that the data bus and the read clock bus are substantially symmetric.

Abstract: A transmission line system for transmitting signals to a means operating at a predetermined clock frequency includes a driver circuit and a transmission line, which comprises an associated terminating impedance. The length of the transmission line and/or the associated terminating impedance is set such that the so established resonance frequency is lower than the predetermined clock frequency.

Abstract: A circuit configuration prevents a transfer of interference signals present on an input line to a processing section. Electrical input signals are evaluated in an analysis circuit which is connected in parallel with the actual reception circuit in a protection device. If an interference signal is present, a transfer circuit is controlled such that a transfer to the processing section is prevented.

Abstract: The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is integrated between a start time and an end time that are specified by a control signal. An integration period between the start time and the end time depends on the frequency of the data signal. The data item is assigned a logic data value based on the result of the integration. The input circuit has a comparator device, an integration device and a switching device. The data signal is first integrated in order to obtain an integration value. The comparator device compares the integration value with a prescribed threshold value. A logic data value is assigned to the data item based on the result of the comparison.

Abstract: An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.

Abstract: The circuit configuration, in particular a DRAM element, has a protection device for suppressing the formation and/or emission of a reflection signal caused by a received supply input signal. An active signal matching device is provided, with which it is possible to prevent the formation of a reflection signal by using the input signal.

Abstract: A circuit configuration prevents a transfer of interference signals present on an input line to a processing section. Electrical input signals are evaluated in an analysis circuit which is connected in parallel with the actual reception circuit in a protection device. If an interference signal is present, a transfer circuit is controlled such that a transfer to the processing section is prevented.

Abstract: The circuit configuration, in particular a DRAM element, has a protection device for suppressing the formation and/or emission of a reflection signal caused by a received supply input signal. An active signal matching device is provided, with which it is possible to prevent the formation of a reflection signal by using the input signal.