Patents by Inventor Andre Schenk
Andre Schenk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9559204Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.Type: GrantFiled: January 13, 2015Date of Patent: January 31, 2017Assignee: Infineon Technologies AGInventors: Helmut Horst Tews, Andre Schenk
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Publication number: 20150123201Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.Type: ApplicationFiled: January 13, 2015Publication date: May 7, 2015Inventors: Helmut Horst Tews, Andre Schenk
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Patent number: 8946034Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.Type: GrantFiled: November 22, 2013Date of Patent: February 3, 2015Assignee: Infineon Technologies AGInventors: Helmut Horst Tews, Andre Schenk
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Publication number: 20140077299Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.Type: ApplicationFiled: November 22, 2013Publication date: March 20, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Helmut Horst Tews, Andre Schenk
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Patent number: 8624334Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.Type: GrantFiled: July 29, 2011Date of Patent: January 7, 2014Assignee: Infineon Technologies AGInventors: Helmut Horst Tews, Andre Schenk
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Publication number: 20110278680Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.Type: ApplicationFiled: July 29, 2011Publication date: November 17, 2011Applicant: Infineon Technologies AGInventors: Helmut Horst Tews, Andre Schenk
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Patent number: 8003470Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.Type: GrantFiled: September 13, 2005Date of Patent: August 23, 2011Assignee: Infineon Technologies AGInventors: Helmut Horst Tews, Andre Schenk
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Publication number: 20070249128Abstract: Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O3-TEOS) to form a layer of O3-TEOS on the substrate, and treating the layer of O3-TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O3-TEOS layer by reducing the amount of water in the layer. Moreover, the UV treatment may also reduce the amount of silanol in the O3-TEOS layer, which can also increase reliability of the device.Type: ApplicationFiled: April 19, 2006Publication date: October 25, 2007Inventors: Junjung Kim, JaeEon Park, Johnny Widodo, Andre Schenk, Alois Gutmann, Roland Hampp
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Patent number: 7219060Abstract: A high quality speech synthesizer in various embodiments concatenates speech waveforms referenced by a large speech database. Speech quality is further improved by speech unit selection and concatenation smoothing.Type: GrantFiled: December 1, 2003Date of Patent: May 15, 2007Assignee: Nuance Communications, Inc.Inventors: Geert Coorman, Filip Deprez, Mario De Bock, Justin Fackrell, Steven Leys, Peter Rutten, Jan De Moortel, Andre Schenk, Bert Van Coile
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Publication number: 20070057324Abstract: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.Type: ApplicationFiled: September 13, 2005Publication date: March 15, 2007Inventors: Helmut Tews, Andre Schenk
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Publication number: 20060004887Abstract: There is disclosed a method and a device for generating distributed applications for each level in a multi-level database environment, comprising: receiving an integrated configuration code comprising code sections for all information required for generating an application in each of said levels, parsing all code sections in said integrated configuration code required for at least one level of said multi-level environment, extracting said parsed code sections for said at least one level, and converting said extracted code sections into level-specific application code for each extracted level.Type: ApplicationFiled: April 4, 2002Publication date: January 5, 2006Inventor: Andre Schenk
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Patent number: 6919264Abstract: A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.Type: GrantFiled: September 5, 2003Date of Patent: July 19, 2005Assignee: Infineon Technologies AGInventors: Axel Brintzinger, Ingo Uhlendorf, Andre Schenk, Alexander Wollanke
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Publication number: 20040111266Abstract: A high quality speech synthesizer in various embodiments concatenates speech waveforms referenced by a large speech database. Speech quality is further improved by speech unit selection and concatenation smoothing.Type: ApplicationFiled: December 1, 2003Publication date: June 10, 2004Inventors: Geert Coorman, Filip Deprez, Mario De Bock, Justin Fackrell, Steven Leys, Peter Rutten, Jan DeMoortel, Andre Schenk, Bert Van Coile
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Publication number: 20040087131Abstract: A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.Type: ApplicationFiled: September 5, 2003Publication date: May 6, 2004Inventors: Axel Brintzinger, Ingo Uhlendorf, Andre Schenk, Alexander Wollanke
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Patent number: 6665641Abstract: A high quality speech synthesizer in various embodiments concatenates speech waveforms referenced by a large speech database. Speech quality is further improved by speech unit selection and concatenation smoothing.Type: GrantFiled: November 12, 1999Date of Patent: December 16, 2003Assignee: ScanSoft, Inc.Inventors: Geert Coorman, Filip Deprez, Mario De Bock, Justin Fackrell, Steven Leys, Peter Rutten, Jan DeMoortel, Andre Schenk, Bert Van Coile