Abstract: An area-efficient fully integrated BiCMOS analog time delay circuit with low-power supply requirements provides delays as long as two milliseconds. An ultralow PTAT current source comprises medium-value resistors to discharge an on-chip capacitor from a fixed zero-temperature coefficient voltage. The comparator monitors the capacitor voltage and changes stage from low to high when the capacitor is discharged below a reference voltage having a defined negative temperature coefficient. The temperature coefficient of the reference voltage generator and the PTAT current source are such that the timeout period is independent of temperature in the first-order. The generated timeout delay is independent of the supply voltage and can be used with a supply voltage as low as two volts.

Abstract: A startup circuit is used for producing a startup current for an analog integrated circuit device. The startup circuit includes a first portion including a diode component and a capacitance component. The first portion is configured to function as a power supply backup and generate a backup point voltage. The startup circuit includes a second portion including a current mirror component and a feedback component. The second portion is configured to generate a startup current using the backup point voltage, such that the startup current is provided based on the backup point voltage as a power supply voltage increases from a power off condition or a transient, thereby keeping an analog circuit alive during transients in power supply for fast recover and operation.

Abstract: A low dropout voltage (LDO) regulator having an adaptive zero frequency circuit is described. The adaptive zero frequency circuit maintains the stability of the LDO regulator and improves the transient response of the LDO regulator under a range of values for the output current, whereas the output current inversely varies with the load resistance coupled to the output of the LDO regulator. The adaptive zero frequency circuit generates a zero having a frequency which varies with the output current. Hence, the frequency of the zero changes to maintain the stability of the LDO regulator despite the variation in the frequency of the low-frequency pole generated by the load resistance and the load capacitance (or output capacitor) coupled to the output of the LDO regulator.